[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #211743)

[Pengcheng Wang via llvm-branch-commits]

wangpc-pp wrote:

> I'm not sure I follow the intent of this change. The PR description makes it sound like an NFC, but in moving `computePSetLimit()` into `TargetRegisterInfo`, you've also started consulting `getRawAllocationOrder()`, causing the (enormous) test diff. I think, at the very least, this patch wants splitting in two: one patch to do the refactor, the other to add the expensive new logic.

There is no massive changes now (I reverted the change in AMDGPU backend). The only suspect is PPC and I explained it in https://github.com/llvm/llvm-project/pull/118787#discussion_r1910032491.

> For these PPC changes, it is just because we have different code path now and the dumps are different.

This PR should have no CodeGen change and is technically NFC except the changes in TableGen.

https://github.com/llvm/llvm-project/pull/211743