[llvm-branch-commits] [llvm] [AMDGPU] Upstream True16 runlines for various tests (PR #209891)

Mon Jul 20 13:00:21 PDT 2026

https://github.com/saxlungs updated https://github.com/llvm/llvm-project/pull/209891

>From 230a8d9fd4348b76296f740bae7e66d57ef8bf81 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Wed, 15 Jul 2026 16:15:39 -0400
Subject: [PATCH] [AMDGPU] Upstream True16 runlines for various tests

---
 .../GlobalISel/llvm.amdgcn.ballot.i32.ll      |    6 +-
 .../llvm.amdgcn.image.atomic.dim.a16.ll       | 3211 +++++++++++++----
 .../llvm.amdgcn.image.gather4.a16.dim.ll      | 1575 ++++++--
 .../llvm.amdgcn.image.load.2darraymsaa.a16.ll |  471 ++-
 .../llvm.amdgcn.image.load.3d.a16.ll          |  427 ++-
 .../llvm.amdgcn.image.sample.g16.ll           |  607 ++--
 .../llvm.amdgcn.raw.buffer.load.tfe.ll        |  700 ++--
 .../llvm.amdgcn.struct.buffer.load.tfe.ll     |  750 ++--
 llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll   |  139 +-
 llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll    |  286 +-
 llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll    |  131 +-
 ...wmma-gfx12-w32-f16-f32-matrix-modifiers.ll |  127 +-
 ...wmma-gfx12-w64-f16-f32-matrix-modifiers.ll |   85 +-
 .../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll |   45 +-
 .../CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll    |    6 +-
 .../CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll    |    6 +-
 .../CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll    |    6 +-
 .../AMDGPU/llvm.amdgcn.raw.buffer.load.ll     |  346 +-
 llvm/test/CodeGen/AMDGPU/load-constant-i1.ll  | 2034 +++++++----
 llvm/test/CodeGen/AMDGPU/mul.ll               |    6 +-
 .../AMDGPU/pseudo-scalar-transcendental.ll    |  225 +-
 21 files changed, 7922 insertions(+), 3267 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
index 048f5710c880c..c1742bff4b06f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgpu10.10 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
-; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX11 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX11-FAKE16 %s
 
 declare i32 @llvm.amdgcn.ballot.i32(i1)
 declare i32 @llvm.ctpop.i32(i32)
@@ -478,3 +479,6 @@ exit:
   store i32 %ballot, ptr addrspace(1) %out
   ret void
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-FAKE16: {{.*}}
+; GFX11-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
index 89f73ba07d58d..fce5fd01065cc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
 ; GFX9-LABEL: atomic_swap_i32_1d:
@@ -37,21 +39,65 @@ define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_swap_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_swap_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_swap_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_swap_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_swap_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -91,21 +137,65 @@ define amdgpu_ps float @atomic_add_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -145,21 +235,65 @@ define amdgpu_ps float @atomic_sub_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_sub_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_sub_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_sub_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_sub_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_sub_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -199,21 +333,65 @@ define amdgpu_ps float @atomic_smin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_smin_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_smin_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_smin_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_smin_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_smin_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -253,21 +431,65 @@ define amdgpu_ps float @atomic_umin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_umin_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_umin_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_umin_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_umin_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_umin_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -307,21 +529,65 @@ define amdgpu_ps float @atomic_smax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_smax_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_smax_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_smax_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_smax_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_smax_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -361,21 +627,65 @@ define amdgpu_ps float @atomic_umax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_umax_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_umax_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_umax_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_umax_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_umax_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -415,21 +725,65 @@ define amdgpu_ps float @atomic_and_i321d(<8 x i32> inreg %rsrc, i32 %data, i16 %
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_and_i321d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_and_i321d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_and_i321d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_and_i321d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_and_i321d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -469,21 +823,65 @@ define amdgpu_ps float @atomic_or_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_or_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_or_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_or_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_or_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_or_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -523,21 +921,65 @@ define amdgpu_ps float @atomic_xor_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_xor_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_xor_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_xor_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_xor_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_xor_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -577,21 +1019,65 @@ define amdgpu_ps float @atomic_inc_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_inc_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_inc_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_inc_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_inc_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_inc_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -631,21 +1117,65 @@ define amdgpu_ps float @atomic_dec_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_dec_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_dec_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_dec_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_dec_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_dec_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -685,21 +1215,65 @@ define amdgpu_ps float @atomic_cmpswap_i32_1d(<8 x i32> inreg %rsrc, i32 %cmp, i
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_cmpswap_i32_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_cmpswap_i32_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_cmpswap_i32_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_cmpswap_i32_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_cmpswap_i32_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i16(i32 %cmp, i32 %swap, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -739,21 +1313,67 @@ define amdgpu_ps float @atomic_add_i32_2d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i16(i32 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -797,23 +1417,71 @@ define amdgpu_ps float @atomic_add_i32_3d(<8 x i32> inreg %rsrc, i32 %data, i16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_3d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_3d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_3d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_3d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_3d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i16(i32 %data, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -857,23 +1525,71 @@ define amdgpu_ps float @atomic_add_i32_cube(<8 x i32> inreg %rsrc, i32 %data, i1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_cube:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_cube:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_cube:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_cube:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_cube:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i16(i32 %data, i16 %s, i16 %t, i16 %face, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -913,21 +1629,67 @@ define amdgpu_ps float @atomic_add_i32_1darray(<8 x i32> inreg %rsrc, i32 %data,
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_1darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_1darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_1darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_1darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_1darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i16(i32 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -971,23 +1733,71 @@ define amdgpu_ps float @atomic_add_i32_2darray(<8 x i32> inreg %rsrc, i32 %data,
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_2darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_2darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_2darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_2darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_2darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -1031,23 +1841,71 @@ define amdgpu_ps float @atomic_add_i32_2dmsaa(<8 x i32> inreg %rsrc, i32 %data,
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_2dmsaa:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_2dmsaa:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_2dmsaa:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_2dmsaa:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_2dmsaa:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -1091,23 +1949,74 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_2darraymsaa:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_2darraymsaa:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v6, v3
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, v[5:6], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_2darraymsaa:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_2darraymsaa:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_2darraymsaa:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i32 %v to float
@@ -1147,21 +2056,65 @@ define amdgpu_ps float @atomic_add_i32_1d_slc(<8 x i32> inreg %rsrc, i32 %data,
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i32_1d_slc:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_1d_slc:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc slc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_1d_slc:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc slc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_1d_slc:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_1d_slc:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
   %out = bitcast i32 %v to float
@@ -1201,21 +2154,65 @@ define amdgpu_ps <2 x float> @atomic_swap_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_swap_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_swap_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_swap_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_swap_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_swap_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.swap.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1255,21 +2252,65 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1309,21 +2350,65 @@ define amdgpu_ps <2 x float> @atomic_sub_i64_1d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_sub_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_sub_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_sub_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_sub v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_sub_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_sub v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_sub_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_sub_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_sub_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_sub_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.sub.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1363,21 +2448,65 @@ define amdgpu_ps <2 x float> @atomic_smin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_smin_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_min_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_smin_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_smin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_smin_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_smin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_smin_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_min_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_smin_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_min_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.smin.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1417,21 +2546,65 @@ define amdgpu_ps <2 x float> @atomic_umin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_umin_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_min_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_umin_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_umin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_umin_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_umin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_umin_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_min_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_umin_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_min_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.umin.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1471,21 +2644,65 @@ define amdgpu_ps <2 x float> @atomic_smax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_smax_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_max_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_smax_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_smax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_smax_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_smax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_smax_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_max_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_smax_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_max_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.smax.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1525,21 +2742,65 @@ define amdgpu_ps <2 x float> @atomic_umax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_umax_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_max_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_umax_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_umax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_umax_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_umax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_umax_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_max_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_umax_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_max_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.umax.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1579,21 +2840,65 @@ define amdgpu_ps <2 x float> @atomic_and_i64_1d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_and_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_and_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_and_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_and_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_and_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.and.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1633,21 +2938,65 @@ define amdgpu_ps <2 x float> @atomic_or_i64_1d(<8 x i32> inreg %rsrc, i64 %data,
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_or_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_or_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_or_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_or_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_or_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.or.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1687,21 +3036,65 @@ define amdgpu_ps <2 x float> @atomic_xor_i64_1d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_xor_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_xor_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_xor_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_xor_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_xor_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.xor.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1741,21 +3134,65 @@ define amdgpu_ps <2 x float> @atomic_inc_i64_1d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_inc_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_inc_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_inc_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_inc v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_inc_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_inc v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_inc_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_inc_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_inc_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_inc_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.inc.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1795,21 +3232,65 @@ define amdgpu_ps <2 x float> @atomic_dec_i64_1d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_dec_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_dec_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_dec_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_dec v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_dec_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_dec v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_dec_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_dec_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_dec_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_dec_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.dec.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1849,21 +3330,65 @@ define amdgpu_ps <2 x float> @atomic_cmpswap_i64_1d(<8 x i32> inreg %rsrc, i64 %
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_cmpswap_i64_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v4, s0, 16, v4
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_cmpswap_i64_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_cmpswap_i64_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, s0, 16, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_cmpswap_i64_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_cmpswap_i64_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v4, s0, 16, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.cmpswap.1d.i64.i16(i64 %cmp, i64 %swap, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1903,21 +3428,67 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.2d.i64.i16(i64 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -1961,23 +3532,71 @@ define amdgpu_ps <2 x float> @atomic_add_i64_3d(<8 x i32> inreg %rsrc, i64 %data
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_3d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_3d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_3d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_3d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_3d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.3d.i64.i16(i64 %data, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -2021,23 +3640,71 @@ define amdgpu_ps <2 x float> @atomic_add_i64_cube(<8 x i32> inreg %rsrc, i64 %da
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_cube:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_cube:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_cube:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_cube:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_cube:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.cube.i64.i16(i64 %data, i16 %s, i16 %t, i16 %face , <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -2077,21 +3744,67 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1darray(<8 x i32> inreg %rsrc, i64
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_1darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_1darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_1darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_1darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_1darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.1darray.i64.i16(i64 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -2135,23 +3848,71 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darray(<8 x i32> inreg %rsrc, i64
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_2darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_2darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_2darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_2darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_2darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.2darray.i64.i16(i64 %data, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -2195,23 +3956,71 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2dmsaa(<8 x i32> inreg %rsrc, i64 %
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_2dmsaa:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_2dmsaa:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_2dmsaa:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_2dmsaa:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_2dmsaa:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.2dmsaa.i64.i16(i64 %data, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -2255,23 +4064,74 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc,
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_2darraymsaa:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_2darraymsaa:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v5.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], v[6:7], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_2darraymsaa:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_2darraymsaa:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_2darraymsaa:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.2darraymsaa.i64.i16(i64 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
   %out = bitcast i64 %v to <2 x float>
@@ -2311,21 +4171,65 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d_slc(<8 x i32> inreg %rsrc, i64 %
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: atomic_add_i64_1d_slc:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i64_1d_slc:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc slc a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i64_1d_slc:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc slc a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i64_1d_slc:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i64_1d_slc:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call i64 @llvm.amdgcn.image.atomic.add.1d.i64.i16(i64 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
   %out = bitcast i64 %v to <2 x float>
@@ -2375,3 +4279,6 @@ declare i64 @llvm.amdgcn.image.atomic.add.2dmsaa.i64.i16(i64, i16, i16, i16, <8
 declare i64 @llvm.amdgcn.image.atomic.add.2darraymsaa.i64.i16(i64, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
 
 attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
index 72645e5d624fb..4a3a0e234162e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX10NSA %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX10NSA %s
-; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
 ; GFX9-LABEL: gather4_2d:
@@ -51,28 +53,95 @@ define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -129,30 +198,99 @@ define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_cube:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_cube:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_cube:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_cube:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_cube:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f16(i32 1, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -209,30 +347,99 @@ define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_2darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_2darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_2darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_2darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_2darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f16(i32 1, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -285,28 +492,95 @@ define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_c_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -363,30 +637,99 @@ define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f16(i32 1, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -443,30 +786,99 @@ define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_c_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -523,30 +935,99 @@ define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_b_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_b_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_b_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_b_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_b_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f16.f16(i32 1, half %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -603,30 +1084,99 @@ define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_c_b_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_b_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_b_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_b_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_b_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f16.f16(i32 1, half %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -687,32 +1237,103 @@ define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_b_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_b_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_b_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_b_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_b_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f16.f16(i32 1, half %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -773,32 +1394,103 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_c_b_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_b_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_b_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_gather4_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_b_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_b_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v4
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f16.f16(i32 1, half %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -849,27 +1541,87 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_l_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    image_gather4_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_l_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_l_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_l_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_l_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    image_gather4_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 1, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -920,27 +1672,87 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_c_l_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_l_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_l_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_l_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_l_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -987,25 +1799,83 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_lz_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_lz_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_lz_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_lz_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_lz_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -1052,25 +1922,83 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX10NSA-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10NSA-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: gather4_c_lz_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    s_mov_b32 s8, s10
-; GFX12-NEXT:    s_mov_b32 s9, s11
-; GFX12-NEXT:    s_mov_b32 s10, s12
-; GFX12-NEXT:    s_mov_b32 s11, s13
-; GFX12-NEXT:    image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_lz_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-TRUE16-NEXT:    image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_lz_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX11-FAKE16-NEXT:    image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_lz_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-TRUE16-NEXT:    image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_lz_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, s12
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, s13
+; GFX12-FAKE16-NEXT:    image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   ret <4 x float> %v
@@ -1092,3 +2020,6 @@ declare <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 immarg, floa
 declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f16(i32 immarg, float, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
 
 attributes #0 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
index 4d1c0341c782c..26a7a9106b3b6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
 ; GFX9-LABEL: load_2darraymsaa_v4f32_xyzw:
@@ -23,41 +25,93 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc,
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10PLUS-LABEL: load_2darraymsaa_v4f32_xyzw:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10PLUS-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10PLUS-NEXT:    s_mov_b32 s0, s2
-; GFX10PLUS-NEXT:    s_mov_b32 s1, s3
-; GFX10PLUS-NEXT:    s_mov_b32 s2, s4
-; GFX10PLUS-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX10PLUS-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
-; GFX10PLUS-NEXT:    s_mov_b32 s3, s5
-; GFX10PLUS-NEXT:    s_mov_b32 s4, s6
-; GFX10PLUS-NEXT:    s_mov_b32 s5, s7
-; GFX10PLUS-NEXT:    s_mov_b32 s6, s8
-; GFX10PLUS-NEXT:    s_mov_b32 s7, s9
-; GFX10PLUS-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0)
-; GFX10PLUS-NEXT:    ; return to shader part epilog
+; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX10-NEXT:    s_mov_b32 s0, s2
+; GFX10-NEXT:    s_mov_b32 s1, s3
+; GFX10-NEXT:    s_mov_b32 s2, s4
+; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
+; GFX10-NEXT:    s_mov_b32 s3, s5
+; GFX10-NEXT:    s_mov_b32 s4, s6
+; GFX10-NEXT:    s_mov_b32 s5, s7
+; GFX10-NEXT:    s_mov_b32 s6, s8
+; GFX10-NEXT:    s_mov_b32 s7, s9
+; GFX10-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_load v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_2darraymsaa_v4f32_xyzw:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_load v[0:3], [v0, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
   %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
   ret <4 x float> %v
 }
@@ -122,63 +176,121 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r
 ; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_mov_b32_e32 v5, 0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    s_mov_b32 s0, s2
-; GFX11-NEXT:    s_mov_b32 s1, s3
-; GFX11-NEXT:    v_mov_b32_e32 v6, v5
-; GFX11-NEXT:    v_mov_b32_e32 v7, v5
-; GFX11-NEXT:    v_mov_b32_e32 v8, v5
-; GFX11-NEXT:    v_mov_b32_e32 v9, v5
-; GFX11-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
-; GFX11-NEXT:    s_mov_b32 s2, s4
-; GFX11-NEXT:    s_mov_b32 s3, s5
-; GFX11-NEXT:    s_mov_b32 s4, s6
-; GFX11-NEXT:    s_mov_b32 s5, s7
-; GFX11-NEXT:    s_mov_b32 s6, s8
-; GFX11-NEXT:    s_mov_b32 s7, s9
-; GFX11-NEXT:    v_mov_b32_e32 v0, v5
-; GFX11-NEXT:    v_mov_b32_e32 v1, v6
-; GFX11-NEXT:    v_mov_b32_e32 v2, v7
-; GFX11-NEXT:    v_mov_b32_e32 v3, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, v7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v8
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v9
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v10
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX11-TRUE16-NEXT:    image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v6
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v7
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v6, v2
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v8, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v11, v7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, v8
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, v9
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, v10
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX12-TRUE16-NEXT:    image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_mov_b32_e32 v5, 0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    v_mov_b32_e32 v6, v5
-; GFX12-NEXT:    v_mov_b32_e32 v7, v5
-; GFX12-NEXT:    v_mov_b32_e32 v8, v5
-; GFX12-NEXT:    v_mov_b32_e32 v9, v5
-; GFX12-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    v_mov_b32_e32 v0, v5
-; GFX12-NEXT:    v_mov_b32_e32 v1, v6
-; GFX12-NEXT:    v_mov_b32_e32 v2, v7
-; GFX12-NEXT:    v_mov_b32_e32 v3, v8
-; GFX12-NEXT:    v_mov_b32_e32 v4, v9
-; GFX12-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v6, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v7, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, v6
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, v7
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v3, v8
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX12-FAKE16-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
   %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
   %v.vec = extractvalue { <4 x float>, i32 } %v, 0
   %v.err = extractvalue { <4 x float>, i32 } %v, 1
@@ -246,63 +358,121 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre
 ; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_mov_b32_e32 v5, 0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    s_mov_b32 s0, s2
-; GFX11-NEXT:    s_mov_b32 s1, s3
-; GFX11-NEXT:    v_mov_b32_e32 v6, v5
-; GFX11-NEXT:    v_mov_b32_e32 v7, v5
-; GFX11-NEXT:    v_mov_b32_e32 v8, v5
-; GFX11-NEXT:    v_mov_b32_e32 v9, v5
-; GFX11-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
-; GFX11-NEXT:    s_mov_b32 s2, s4
-; GFX11-NEXT:    s_mov_b32 s3, s5
-; GFX11-NEXT:    s_mov_b32 s4, s6
-; GFX11-NEXT:    s_mov_b32 s5, s7
-; GFX11-NEXT:    s_mov_b32 s6, s8
-; GFX11-NEXT:    s_mov_b32 s7, s9
-; GFX11-NEXT:    v_mov_b32_e32 v0, v5
-; GFX11-NEXT:    v_mov_b32_e32 v1, v6
-; GFX11-NEXT:    v_mov_b32_e32 v2, v7
-; GFX11-NEXT:    v_mov_b32_e32 v3, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, v7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v8
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v9
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v10
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX11-TRUE16-NEXT:    image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v6
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v7
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v6, v2
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v8, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v11, v7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v7
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, v8
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, v9
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, v10
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX12-TRUE16-NEXT:    image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_mov_b32_e32 v5, 0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    v_mov_b32_e32 v6, v5
-; GFX12-NEXT:    v_mov_b32_e32 v7, v5
-; GFX12-NEXT:    v_mov_b32_e32 v8, v5
-; GFX12-NEXT:    v_mov_b32_e32 v9, v5
-; GFX12-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    v_mov_b32_e32 v0, v5
-; GFX12-NEXT:    v_mov_b32_e32 v1, v6
-; GFX12-NEXT:    v_mov_b32_e32 v2, v7
-; GFX12-NEXT:    v_mov_b32_e32 v3, v8
-; GFX12-NEXT:    v_mov_b32_e32 v4, v9
-; GFX12-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v6, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v7, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v11, v3, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, v5
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, v6
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, v7
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v3, v8
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX12-FAKE16-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
   %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 3, i32 0)
   %v.vec = extractvalue { <4 x float>, i32 } %v, 0
   %v.err = extractvalue { <4 x float>, i32 } %v, 1
@@ -314,3 +484,6 @@ declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 immarg, i1
 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
 
 attributes #0 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
index e0b7c32d24993..2c0ee1740375a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %r) {
 ; GFX9-LABEL: load_3d_v4f32_xyzw:
@@ -23,41 +25,89 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s,
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10PLUS-LABEL: load_3d_v4f32_xyzw:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10PLUS-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10PLUS-NEXT:    s_mov_b32 s0, s2
-; GFX10PLUS-NEXT:    s_mov_b32 s1, s3
-; GFX10PLUS-NEXT:    s_mov_b32 s2, s4
-; GFX10PLUS-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX10PLUS-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX10PLUS-NEXT:    s_mov_b32 s3, s5
-; GFX10PLUS-NEXT:    s_mov_b32 s4, s6
-; GFX10PLUS-NEXT:    s_mov_b32 s5, s7
-; GFX10PLUS-NEXT:    s_mov_b32 s6, s8
-; GFX10PLUS-NEXT:    s_mov_b32 s7, s9
-; GFX10PLUS-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0)
-; GFX10PLUS-NEXT:    ; return to shader part epilog
+; GFX10-LABEL: load_3d_v4f32_xyzw:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX10-NEXT:    s_mov_b32 s0, s2
+; GFX10-NEXT:    s_mov_b32 s1, s3
+; GFX10-NEXT:    s_mov_b32 s2, s4
+; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX10-NEXT:    s_mov_b32 s3, s5
+; GFX10-NEXT:    s_mov_b32 s4, s6
+; GFX10-NEXT:    s_mov_b32 s5, s7
+; GFX10-NEXT:    s_mov_b32 s6, s8
+; GFX10-NEXT:    s_mov_b32 s7, s9
+; GFX10-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: load_3d_v4f32_xyzw:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    image_load v[0:3], [v0, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: load_3d_v4f32_xyzw:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_3d_v4f32_xyzw:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-TRUE16-LABEL: load_3d_v4f32_xyzw:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    image_load v[0:3], [v0, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: load_3d_v4f32_xyzw:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
   %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
   ret <4 x float> %v
 }
@@ -122,57 +172,107 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr
 ; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: load_3d_v4f32_xyzw_tfe:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    s_mov_b32 s0, s2
-; GFX11-NEXT:    s_mov_b32 s1, s3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_mov_b32_e32 v6, v5
-; GFX11-NEXT:    v_mov_b32_e32 v7, v5
-; GFX11-NEXT:    v_mov_b32_e32 v8, v5
-; GFX11-NEXT:    v_mov_b32_e32 v9, v5
-; GFX11-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
-; GFX11-NEXT:    s_mov_b32 s2, s4
-; GFX11-NEXT:    s_mov_b32 s3, s5
-; GFX11-NEXT:    s_mov_b32 s4, s6
-; GFX11-NEXT:    s_mov_b32 s5, s7
-; GFX11-NEXT:    s_mov_b32 s6, s8
-; GFX11-NEXT:    s_mov_b32 s7, s9
-; GFX11-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
-; GFX11-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, v7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX11-TRUE16-NEXT:    image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v11, v7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX12-TRUE16-NEXT:    image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_3d_v4f32_xyzw_tfe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v9, v5
-; GFX12-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v5
-; GFX12-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
-; GFX12-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
-; GFX12-NEXT:    v_mov_b32_e32 v4, v9
-; GFX12-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v9, v5
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX12-FAKE16-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
   %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 1, i32 0)
   %v.vec = extractvalue { <4 x float>, i32 } %v, 0
   %v.err = extractvalue { <4 x float>, i32 } %v, 1
@@ -240,57 +340,107 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc,
 ; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    s_mov_b32 s0, s2
-; GFX11-NEXT:    s_mov_b32 s1, s3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_mov_b32_e32 v6, v5
-; GFX11-NEXT:    v_mov_b32_e32 v7, v5
-; GFX11-NEXT:    v_mov_b32_e32 v8, v5
-; GFX11-NEXT:    v_mov_b32_e32 v9, v5
-; GFX11-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
-; GFX11-NEXT:    s_mov_b32 s2, s4
-; GFX11-NEXT:    s_mov_b32 s3, s5
-; GFX11-NEXT:    s_mov_b32 s4, s6
-; GFX11-NEXT:    s_mov_b32 s5, s7
-; GFX11-NEXT:    s_mov_b32 s6, s8
-; GFX11-NEXT:    s_mov_b32 s7, s9
-; GFX11-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
-; GFX11-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, v7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX11-TRUE16-NEXT:    image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v7, 0
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v1.l
+; GFX12-TRUE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v11, v7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, v11
+; GFX12-TRUE16-NEXT:    image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b32 v7, v4, s[10:11]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_mov_b32 s0, s2
-; GFX12-NEXT:    s_mov_b32 s1, s3
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v9, v5
-; GFX12-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v5
-; GFX12-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
-; GFX12-NEXT:    s_mov_b32 s2, s4
-; GFX12-NEXT:    s_mov_b32 s3, s5
-; GFX12-NEXT:    s_mov_b32 s4, s6
-; GFX12-NEXT:    s_mov_b32 s5, s7
-; GFX12-NEXT:    s_mov_b32 s6, s8
-; GFX12-NEXT:    s_mov_b32 s7, s9
-; GFX12-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
-; GFX12-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
-; GFX12-NEXT:    v_mov_b32_e32 v4, v9
-; GFX12-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b32 v5, v4, s[10:11]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v9, v5
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v10, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v11, s0, 16, v2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX12-FAKE16-NEXT:    image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b32 v5, v4, s[10:11]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
   %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 3, i32 0)
   %v.vec = extractvalue { <4 x float>, i32 } %v, 0
   %v.err = extractvalue { <4 x float>, i32 } %v, 1
@@ -302,3 +452,6 @@ declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 immarg, i16, i16, i
 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
 
 attributes #0 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
index 9225426521a11..8f99ace9dd94c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
@@ -1,7 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
 ; GFX10-LABEL: sample_d_1d:
@@ -14,25 +16,37 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -49,25 +63,41 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -88,33 +118,49 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_3d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX11-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT:    v_lshl_or_b32 v3, s0, 16, v5
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_3d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
-; GFX12-NEXT:    v_lshl_or_b32 v5, s0, 16, v5
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_3d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_3d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, s0, 16, v5
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_3d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_3d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v5, s0, 16, v5
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -131,25 +177,37 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX11-NEXT:    image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -166,25 +224,41 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
-; GFX12-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX12-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -201,25 +275,37 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, s0, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -236,25 +322,41 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX12-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
-; GFX12-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
+; GFX12-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -271,25 +373,37 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX11-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
-; GFX12-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX11-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, s0, 16, v2
+; GFX12-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -308,25 +422,41 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
-; GFX12-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v4, 16, v3
+; GFX12-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -347,25 +477,43 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V1:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_o_2darray_V1:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v5, v5, 16, v4
-; GFX12-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v5, v4
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v9.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v5, v5, 16, v4
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret float %v
@@ -386,25 +534,43 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V2:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_o_2darray_V2:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX12-NEXT:    v_lshl_or_b32 v5, v5, 16, v4
-; GFX12-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v3, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v5, v4
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v9.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v5, v5, 16, v4
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <2 x float> %v
@@ -426,3 +592,6 @@ declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
 attributes #2 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
index 4c92b06b86836..0d0ab1388c0d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
@@ -4,8 +4,10 @@
 ; RUN: llc -global-isel -mtriple=amdgpu8.03-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX8
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910
 ; RUN: llc -global-isel -mtriple=amdgpu10.10-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910
-; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu11.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11
-; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu12.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1200
+; RUN: llc -global-isel -mattr=+real-true16 -mtriple=amdgpu11.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE16
+; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu11.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE16
+; RUN: llc -global-isel -mattr=+real-true16 -mtriple=amdgpu12.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX12,GFX12-TRUE16
+; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu12.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX12,GFX12-FAKE16
 ; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu12.50-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1250
 
 define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %data_addr, ptr addrspace(1) %tfe_addr) {
@@ -111,27 +113,27 @@ define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspa
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_i8_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_BYTE [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i8) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_i8_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   GLOBAL_STORE_BYTE [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i8) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_i8_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -242,50 +244,101 @@ define amdgpu_ps void @raw_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
   ; GFX910-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX910-NEXT:   S_ENDPGM 0
   ;
-  ; GFX11-LABEL: name: raw_buffer_load_i16_tfe
-  ; GFX11: bb.1 (%ir-block.0):
-  ; GFX11-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX11-NEXT: {{  $}}
-  ; GFX11-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX11-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX11-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX11-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX11-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX11-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX11-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX11-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX11-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX11-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX11-NEXT:   [[BUFFER_LOAD_USHORT_TFE_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
-  ; GFX11-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub0
-  ; GFX11-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
-  ; GFX11-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
-  ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX11-NEXT:   S_ENDPGM 0
+  ; GFX11-TRUE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX11-TRUE16: bb.1 (%ir-block.0):
+  ; GFX11-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-TRUE16-NEXT: {{  $}}
+  ; GFX11-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX11-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub0
+  ; GFX11-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
+  ; GFX11-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX11-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX11-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX11-FAKE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX11-FAKE16: bb.1 (%ir-block.0):
+  ; GFX11-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-FAKE16-NEXT: {{  $}}
+  ; GFX11-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX11-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub0
+  ; GFX11-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX12-TRUE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX12-TRUE16: bb.1 (%ir-block.0):
+  ; GFX12-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-TRUE16-NEXT: {{  $}}
+  ; GFX12-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX12-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX12-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_i16_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-FAKE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX12-FAKE16: bb.1 (%ir-block.0):
+  ; GFX12-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-FAKE16-NEXT: {{  $}}
+  ; GFX12-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX12-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_i16_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -396,50 +449,101 @@ define amdgpu_ps void @raw_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
   ; GFX910-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX910-NEXT:   S_ENDPGM 0
   ;
-  ; GFX11-LABEL: name: raw_buffer_load_f16_tfe
-  ; GFX11: bb.1 (%ir-block.0):
-  ; GFX11-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX11-NEXT: {{  $}}
-  ; GFX11-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX11-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX11-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX11-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX11-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX11-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX11-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX11-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX11-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX11-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX11-NEXT:   [[BUFFER_LOAD_USHORT_TFE_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
-  ; GFX11-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub0
-  ; GFX11-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
-  ; GFX11-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
-  ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX11-NEXT:   S_ENDPGM 0
+  ; GFX11-TRUE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX11-TRUE16: bb.1 (%ir-block.0):
+  ; GFX11-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-TRUE16-NEXT: {{  $}}
+  ; GFX11-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX11-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub0
+  ; GFX11-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
+  ; GFX11-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX11-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX11-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX11-FAKE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX11-FAKE16: bb.1 (%ir-block.0):
+  ; GFX11-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-FAKE16-NEXT: {{  $}}
+  ; GFX11-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX11-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub0
+  ; GFX11-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX12-TRUE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX12-TRUE16: bb.1 (%ir-block.0):
+  ; GFX12-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-TRUE16-NEXT: {{  $}}
+  ; GFX12-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX12-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX12-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_f16_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-FAKE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX12-FAKE16: bb.1 (%ir-block.0):
+  ; GFX12-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-FAKE16-NEXT: {{  $}}
+  ; GFX12-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX12-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_f16_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -573,27 +677,27 @@ define amdgpu_ps void @raw_buffer_load_i32_tfe(<4 x i32> inreg %rsrc, ptr addrsp
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i32), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i32) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i32), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (i32) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -747,32 +851,32 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v2i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x i32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x i32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v2i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x i32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x i32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v2i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -931,32 +1035,32 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v2f32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v2f32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v2f32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1172,34 +1276,34 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v3i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x i32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x i32>) into %ir.data_addr, align 16, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v3i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x i32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x i32>) into %ir.data_addr, align 16, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v3i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1415,34 +1519,34 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v3f32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x f32>) into %ir.data_addr, align 16, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v3f32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x f32>) into %ir.data_addr, align 16, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v3f32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1619,36 +1723,36 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v4i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x i32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x i32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v4i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x i32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x i32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v4i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1827,36 +1931,36 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v4f32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub0
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub1
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x f32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v4f32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub0
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub1
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x f32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v4f32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
index d8f5c92152f9e..81a44835c2c1e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
@@ -4,8 +4,10 @@
 ; RUN: llc -global-isel -mtriple=amdgpu8.03-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX8
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910
 ; RUN: llc -global-isel -mtriple=amdgpu10.10-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910
-; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu11.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11
-; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu12.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1200
+; RUN: llc -global-isel -mattr=+real-true16 -mtriple=amdgpu11.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE16
+; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu11.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE16
+; RUN: llc -global-isel -mattr=+real-true16 -mtriple=amdgpu12.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX12,GFX12-TRUE16
+; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu12.00-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX12,GFX12-FAKE16
 ; RUN: llc -global-isel -mattr=-real-true16 -mtriple=amdgpu12.50-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1250
 
 define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %data_addr, ptr addrspace(1) %tfe_addr) {
@@ -115,29 +117,29 @@ define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspa
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_i8_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_BYTE [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i8) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_i8_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   GLOBAL_STORE_BYTE [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i8) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_i8_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -253,53 +255,107 @@ define amdgpu_ps void @raw_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
   ; GFX910-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX910-NEXT:   S_ENDPGM 0
   ;
-  ; GFX11-LABEL: name: raw_buffer_load_i16_tfe
-  ; GFX11: bb.1 (%ir-block.0):
-  ; GFX11-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX11-NEXT: {{  $}}
-  ; GFX11-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX11-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX11-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX11-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX11-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX11-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX11-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX11-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX11-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX11-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX11-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX11-NEXT:   [[BUFFER_LOAD_USHORT_TFE_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
-  ; GFX11-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub0
-  ; GFX11-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
-  ; GFX11-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
-  ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX11-NEXT:   S_ENDPGM 0
+  ; GFX11-TRUE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX11-TRUE16: bb.1 (%ir-block.0):
+  ; GFX11-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-TRUE16-NEXT: {{  $}}
+  ; GFX11-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX11-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX11-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub0
+  ; GFX11-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
+  ; GFX11-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX11-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX11-TRUE16-NEXT:   [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX11-FAKE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX11-FAKE16: bb.1 (%ir-block.0):
+  ; GFX11-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-FAKE16-NEXT: {{  $}}
+  ; GFX11-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX11-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX11-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub0
+  ; GFX11-FAKE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX12-TRUE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX12-TRUE16: bb.1 (%ir-block.0):
+  ; GFX12-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-TRUE16-NEXT: {{  $}}
+  ; GFX12-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX12-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX12-TRUE16-NEXT:   [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_i16_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-FAKE16-LABEL: name: raw_buffer_load_i16_tfe
+  ; GFX12-FAKE16: bb.1 (%ir-block.0):
+  ; GFX12-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-FAKE16-NEXT: {{  $}}
+  ; GFX12-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
+  ; GFX12-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-FAKE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_i16_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -415,53 +471,107 @@ define amdgpu_ps void @raw_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
   ; GFX910-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX910-NEXT:   S_ENDPGM 0
   ;
-  ; GFX11-LABEL: name: raw_buffer_load_f16_tfe
-  ; GFX11: bb.1 (%ir-block.0):
-  ; GFX11-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX11-NEXT: {{  $}}
-  ; GFX11-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX11-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX11-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX11-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX11-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX11-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX11-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX11-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX11-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX11-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX11-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX11-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX11-NEXT:   [[BUFFER_LOAD_USHORT_TFE_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
-  ; GFX11-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub0
-  ; GFX11-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
-  ; GFX11-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
-  ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX11-NEXT:   S_ENDPGM 0
+  ; GFX11-TRUE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX11-TRUE16: bb.1 (%ir-block.0):
+  ; GFX11-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-TRUE16-NEXT: {{  $}}
+  ; GFX11-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-TRUE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX11-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX11-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub0
+  ; GFX11-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
+  ; GFX11-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX11-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX11-TRUE16-NEXT:   [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX11-FAKE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX11-FAKE16: bb.1 (%ir-block.0):
+  ; GFX11-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX11-FAKE16-NEXT: {{  $}}
+  ; GFX11-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX11-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX11-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX11-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX11-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX11-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX11-FAKE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX11-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX11-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX11-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub0
+  ; GFX11-FAKE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX11-FAKE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GFX12-TRUE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX12-TRUE16: bb.1 (%ir-block.0):
+  ; GFX12-TRUE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-TRUE16-NEXT: {{  $}}
+  ; GFX12-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-TRUE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-TRUE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-TRUE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-TRUE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-TRUE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-TRUE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX12-TRUE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-TRUE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-TRUE16-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-TRUE16-NEXT:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
+  ; GFX12-TRUE16-NEXT:   [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-TRUE16-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_f16_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-FAKE16-LABEL: name: raw_buffer_load_f16_tfe
+  ; GFX12-FAKE16: bb.1 (%ir-block.0):
+  ; GFX12-FAKE16-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-FAKE16-NEXT: {{  $}}
+  ; GFX12-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-FAKE16-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-FAKE16-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-FAKE16-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-FAKE16-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-FAKE16-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-FAKE16-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-FAKE16-NEXT:   [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8)
+  ; GFX12-FAKE16-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-FAKE16-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_SHORT [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_f16_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -601,29 +711,29 @@ define amdgpu_ps void @raw_buffer_load_i32_tfe(<4 x i32> inreg %rsrc, ptr addrsp
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i32), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (i32), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -783,34 +893,34 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v2i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x i32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x i32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v2i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x i32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x i32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v2i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -975,34 +1085,34 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v2f32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v2f32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v2f32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1225,36 +1335,36 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v3i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x i32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
-  ; GFX1200-NEXT:   [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x i32>) into %ir.data_addr, align 16, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v3i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x i32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
+  ; GFX12-NEXT:   [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x i32>) into %ir.data_addr, align 16, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v3i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1477,36 +1587,36 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v3f32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
-  ; GFX1200-NEXT:   [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x f32>) into %ir.data_addr, align 16, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v3f32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2
+  ; GFX12-NEXT:   [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x f32>) into %ir.data_addr, align 16, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v3f32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1689,38 +1799,38 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v4i32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x i32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3
-  ; GFX1200-NEXT:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x i32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v4i32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x i32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3
+  ; GFX12-NEXT:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x i32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v4i32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
@@ -1905,38 +2015,38 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr
   ; GFX11-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
   ; GFX11-NEXT:   S_ENDPGM 0
   ;
-  ; GFX1200-LABEL: name: raw_buffer_load_v4f32_tfe
-  ; GFX1200: bb.1 (%ir-block.0):
-  ; GFX1200-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
-  ; GFX1200-NEXT: {{  $}}
-  ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-  ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
-  ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-  ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-  ; GFX1200-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
-  ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-  ; GFX1200-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
-  ; GFX1200-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
-  ; GFX1200-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-  ; GFX1200-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
-  ; GFX1200-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8)
-  ; GFX1200-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub0
-  ; GFX1200-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub1
-  ; GFX1200-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2
-  ; GFX1200-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3
-  ; GFX1200-NEXT:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
-  ; GFX1200-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
-  ; GFX1200-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
-  ; GFX1200-NEXT:   [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x f32>) into %ir.data_addr, addrspace 1)
-  ; GFX1200-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
-  ; GFX1200-NEXT:   S_ENDPGM 0
+  ; GFX12-LABEL: name: raw_buffer_load_v4f32_tfe
+  ; GFX12: bb.1 (%ir-block.0):
+  ; GFX12-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX12-NEXT: {{  $}}
+  ; GFX12-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GFX12-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+  ; GFX12-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+  ; GFX12-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+  ; GFX12-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+  ; GFX12-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+  ; GFX12-NEXT:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+  ; GFX12-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+  ; GFX12-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+  ; GFX12-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+  ; GFX12-NEXT:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+  ; GFX12-NEXT:   [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN:%[0-9]+]]:vreg_160 = BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN [[COPY8]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8)
+  ; GFX12-NEXT:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub0
+  ; GFX12-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub1
+  ; GFX12-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2
+  ; GFX12-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3
+  ; GFX12-NEXT:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+  ; GFX12-NEXT:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+  ; GFX12-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+  ; GFX12-NEXT:   [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]]
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x f32>) into %ir.data_addr, addrspace 1)
+  ; GFX12-NEXT:   GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
+  ; GFX12-NEXT:   S_ENDPGM 0
   ;
   ; GFX1250-LABEL: name: raw_buffer_load_v4f32_tfe
   ; GFX1250: bb.1 (%ir-block.0):
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index df0f8a9e6a9cb..344e16addf8a9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
 
 define i8 @v_lshr_i8(i8 %value, i8 %amount) {
 ; GFX6-LABEL: v_lshr_i8:
@@ -26,13 +27,29 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
 ; GFX9-NEXT:    v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_lshr_i8:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, v1, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_lshr_i8:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX10-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_lshr_i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_lshr_i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i8 %value, %amount
   ret i8 %result
 }
@@ -58,12 +75,26 @@ define i8 @v_lshr_i8_7(i8 %value) {
 ; GFX9-NEXT:    v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_lshr_i8_7:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 7, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_lshr_i8_7:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, 7, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_lshr_i8_7:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, 7, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_lshr_i8_7:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, 7, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i8 %value, 7
   ret i8 %result
 }
@@ -615,11 +646,23 @@ define i16 @v_lshr_i16(i16 %value, i16 %amount) {
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_lshr_i16:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, v1, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_lshr_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_lshrrev_b16 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_lshr_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_lshr_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i16 %value, %amount
   ret i16 %result
 }
@@ -643,11 +686,23 @@ define i16 @v_lshr_i16_15(i16 %value) {
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 15, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_lshr_i16_15:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 15, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_lshr_i16_15:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_lshrrev_b16 v0, 15, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_lshr_i16_15:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, 15, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_lshr_i16_15:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, 15, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i16 %value, 15
   ret i16 %result
 }
@@ -725,10 +780,20 @@ define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {
 ; GFX9-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10PLUS-LABEL: lshr_i16_sv:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, v0, s0
-; GFX10PLUS-NEXT:    ; return to shader part epilog
+; GFX10-LABEL: lshr_i16_sv:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshrrev_b16 v0, v0, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: lshr_i16_sv:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, v0.l, s0
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: lshr_i16_sv:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, v0, s0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %result = lshr i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
@@ -752,10 +817,20 @@ define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) {
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10PLUS-LABEL: lshr_i16_vs:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, s0, v0
-; GFX10PLUS-NEXT:    ; return to shader part epilog
+; GFX10-LABEL: lshr_i16_vs:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshrrev_b16 v0, s0, v0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: lshr_i16_vs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, s0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: lshr_i16_vs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, s0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %result = lshr i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
index 73695793e8faf..72ad3837e0c37 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -3,11 +3,14 @@
 ; RUN: llc -global-isel -mtriple=amdgpu8.01 < %s | FileCheck -check-prefixes=GCN,GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16, -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16, -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
-; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12 %s
-; RUN: llc -global-isel -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250 %s
-; RUN: llc -global-isel -mtriple=amdgpu13.10 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX13 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu13.10 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX13,GFX13-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu13.10 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX13,GFX13-FAKE16 %s
 
 define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) {
 ; GCN-LABEL: s_mul_i16:
@@ -80,32 +83,59 @@ define i16 @v_mul_i16(i16 %num, i16 %den) {
 ; GFX11-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_mul_i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: v_mul_i16:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-;
-; GFX13-LABEL: v_mul_i16:
-; GFX13:       ; %bb.0:
-; GFX13-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX13-NEXT:    s_wait_expcnt 0x0
-; GFX13-NEXT:    s_wait_samplecnt 0x0
-; GFX13-NEXT:    s_wait_bvhcnt 0x0
-; GFX13-NEXT:    s_wait_kmcnt 0x0
-; GFX13-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX13-NEXT:    s_set_pc_i64 s[30:31]
+; GFX12-TRUE16-LABEL: v_mul_i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_mul_i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: v_mul_i16:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX1250-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: v_mul_i16:
+; GFX1250-FAKE16:       ; %bb.0:
+; GFX1250-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX1250-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX13-TRUE16-LABEL: v_mul_i16:
+; GFX13-TRUE16:       ; %bb.0:
+; GFX13-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX13-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX13-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX13-FAKE16-LABEL: v_mul_i16:
+; GFX13-FAKE16:       ; %bb.0:
+; GFX13-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX13-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX13-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
   %result = mul i16 %num, %den
   ret i16 %result
 }
@@ -203,38 +233,71 @@ define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) {
 ; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_mul_i16_zeroext:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: v_mul_i16_zeroext:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-;
-; GFX13-LABEL: v_mul_i16_zeroext:
-; GFX13:       ; %bb.0:
-; GFX13-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX13-NEXT:    s_wait_expcnt 0x0
-; GFX13-NEXT:    s_wait_samplecnt 0x0
-; GFX13-NEXT:    s_wait_bvhcnt 0x0
-; GFX13-NEXT:    s_wait_kmcnt 0x0
-; GFX13-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX13-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX13-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX13-NEXT:    s_set_pc_i64 s[30:31]
+; GFX12-TRUE16-LABEL: v_mul_i16_zeroext:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_mul_i16_zeroext:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: v_mul_i16_zeroext:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
+; GFX1250-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: v_mul_i16_zeroext:
+; GFX1250-FAKE16:       ; %bb.0:
+; GFX1250-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1250-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX13-TRUE16-LABEL: v_mul_i16_zeroext:
+; GFX13-TRUE16:       ; %bb.0:
+; GFX13-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX13-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX13-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX13-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
+; GFX13-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX13-FAKE16-LABEL: v_mul_i16_zeroext:
+; GFX13-FAKE16:       ; %bb.0:
+; GFX13-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX13-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX13-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX13-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX13-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
   %result = mul i16 %num, %den
   ret i16 %result
 }
@@ -324,38 +387,71 @@ define signext i16 @v_mul_i16_signext(i16 signext %num, i16 signext %den) {
 ; GFX11-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
 ; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_mul_i16_signext:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: v_mul_i16_signext:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-;
-; GFX13-LABEL: v_mul_i16_signext:
-; GFX13:       ; %bb.0:
-; GFX13-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX13-NEXT:    s_wait_expcnt 0x0
-; GFX13-NEXT:    s_wait_samplecnt 0x0
-; GFX13-NEXT:    s_wait_bvhcnt 0x0
-; GFX13-NEXT:    s_wait_kmcnt 0x0
-; GFX13-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX13-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX13-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX13-NEXT:    s_set_pc_i64 s[30:31]
+; GFX12-TRUE16-LABEL: v_mul_i16_signext:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_mul_i16_signext:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: v_mul_i16_signext:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX1250-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: v_mul_i16_signext:
+; GFX1250-FAKE16:       ; %bb.0:
+; GFX1250-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX1250-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX13-TRUE16-LABEL: v_mul_i16_signext:
+; GFX13-TRUE16:       ; %bb.0:
+; GFX13-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX13-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX13-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX13-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX13-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX13-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX13-FAKE16-LABEL: v_mul_i16_signext:
+; GFX13-FAKE16:       ; %bb.0:
+; GFX13-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX13-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX13-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX13-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX13-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX13-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
   %result = mul i16 %num, %den
   ret i16 %result
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
index d1df5a02dfc75..e4035042e9ca0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
 
 define i8 @v_shl_i8(i8 %value, i8 %amount) {
 ; GFX6-LABEL: v_shl_i8:
@@ -25,12 +26,26 @@ define i8 @v_shl_i8(i8 %value, i8 %amount) {
 ; GFX9-NEXT:    v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_shl_i8:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, v1, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_shl_i8:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_shl_i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_shl_i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = shl i8 %value, %amount
   ret i8 %result
 }
@@ -54,11 +69,23 @@ define i8 @v_shl_i8_7(i8 %value) {
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 7, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_shl_i8_7:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 7, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_shl_i8_7:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_lshlrev_b16 v0, 7, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_shl_i8_7:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 7, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_shl_i8_7:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 7, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = shl i8 %value, 7
   ret i8 %result
 }
@@ -582,11 +609,23 @@ define i16 @v_shl_i16(i16 %value, i16 %amount) {
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_shl_i16:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, v1, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_shl_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_lshlrev_b16 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_shl_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_shl_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = shl i16 %value, %amount
   ret i16 %result
 }
@@ -610,11 +649,23 @@ define i16 @v_shl_i16_15(i16 %value) {
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 15, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_shl_i16_15:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 15, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_shl_i16_15:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_lshlrev_b16 v0, 15, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_shl_i16_15:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 15, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_shl_i16_15:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 15, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = shl i16 %value, 15
   ret i16 %result
 }
@@ -664,10 +715,20 @@ define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) {
 ; GFX9-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10PLUS-LABEL: shl_i16_sv:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, v0, s0
-; GFX10PLUS-NEXT:    ; return to shader part epilog
+; GFX10-LABEL: shl_i16_sv:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshlrev_b16 v0, v0, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: shl_i16_sv:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.l, s0
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: shl_i16_sv:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v0, s0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %result = shl i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
@@ -690,10 +751,20 @@ define amdgpu_ps half @shl_i16_vs(i16 %value, i16 inreg %amount) {
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10PLUS-LABEL: shl_i16_vs:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, s0, v0
-; GFX10PLUS-NEXT:    ; return to shader part epilog
+; GFX10-LABEL: shl_i16_vs:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_lshlrev_b16 v0, s0, v0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: shl_i16_vs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, s0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: shl_i16_vs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, s0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %result = shl i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
index 33cdab2bdc632..8241d2b7109dc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu11.70 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX1170
-; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX12
+; RUN: llc -global-isel -mtriple=amdgpu11.70 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX1170,GFX1170-TRUE16
+; RUN: llc -global-isel -mtriple=amdgpu11.70 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX1170,GFX1170-FAKE16
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX12,GFX12-TRUE16
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX12,GFX12-FAKE16
 
 define amdgpu_ps void @test_wmma_f32_16x16x16_f16_negA(<8 x half> %A, <8 x half> %B, <8 x float> %C, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_wmma_f32_16x16x16_f16_negA:
@@ -405,47 +407,85 @@ bb:
 ; pack f16 elements with v_perm_b32 since they don't come from same b32
 
 define amdgpu_ps void @test_wmma_f16_16x16x16_f16_negC_pack(<8 x half> %A, <8 x half> %B, ptr %Caddr, ptr addrspace(1) %out) {
-; GFX1170-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
-; GFX1170:       ; %bb.0: ; %bb
-; GFX1170-NEXT:    s_clause 0x1
-; GFX1170-NEXT:    flat_load_b128 v[12:15], v[8:9]
-; GFX1170-NEXT:    flat_load_b128 v[16:19], v[8:9] offset:16
-; GFX1170-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
-; GFX1170-NEXT:    v_and_b32_e32 v8, 0xffff, v12
-; GFX1170-NEXT:    v_and_b32_e32 v9, 0xffff, v14
-; GFX1170-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX1170-NEXT:    v_and_b32_e32 v14, 0xffff, v16
-; GFX1170-NEXT:    v_and_b32_e32 v16, 0xffff, v18
-; GFX1170-NEXT:    v_lshl_or_b32 v12, v13, 16, v8
-; GFX1170-NEXT:    v_lshl_or_b32 v13, v15, 16, v9
-; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-NEXT:    v_lshl_or_b32 v14, v17, 16, v14
-; GFX1170-NEXT:    v_lshl_or_b32 v15, v19, 16, v16
-; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT:    v_wmma_f16_16x16x16_f16 v[12:15], v[0:3], v[4:7], v[12:15] neg_lo:[0,0,1]
-; GFX1170-NEXT:    global_store_b128 v[10:11], v[12:15], off
-; GFX1170-NEXT:    s_endpgm
+; GFX1170-TRUE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX1170-TRUE16:       ; %bb.0: ; %bb
+; GFX1170-TRUE16-NEXT:    s_clause 0x1
+; GFX1170-TRUE16-NEXT:    flat_load_b128 v[12:15], v[8:9]
+; GFX1170-TRUE16-NEXT:    flat_load_b128 v[16:19], v[8:9] offset:16
+; GFX1170-TRUE16-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
+; GFX1170-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v15.l
+; GFX1170-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v17.l
+; GFX1170-TRUE16-NEXT:    v_mov_b16_e32 v18.h, v19.l
+; GFX1170-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v13.l
+; GFX1170-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1170-TRUE16-NEXT:    v_dual_mov_b32 v13, v14 :: v_dual_mov_b32 v14, v16
+; GFX1170-TRUE16-NEXT:    v_mov_b32_e32 v15, v18
+; GFX1170-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT:    v_wmma_f16_16x16x16_f16 v[12:15], v[0:3], v[4:7], v[12:15] neg_lo:[0,0,1]
+; GFX1170-TRUE16-NEXT:    global_store_b128 v[10:11], v[12:15], off
+; GFX1170-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
-; GFX12:       ; %bb.0: ; %bb
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    flat_load_b128 v[12:15], v[8:9]
-; GFX12-NEXT:    flat_load_b128 v[16:19], v[8:9] offset:16
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x101
-; GFX12-NEXT:    v_and_b32_e32 v8, 0xffff, v12
-; GFX12-NEXT:    v_and_b32_e32 v9, 0xffff, v14
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v14, 0xffff, v16
-; GFX12-NEXT:    v_and_b32_e32 v16, 0xffff, v18
-; GFX12-NEXT:    v_lshl_or_b32 v12, v13, 16, v8
-; GFX12-NEXT:    v_lshl_or_b32 v13, v15, 16, v9
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-NEXT:    v_lshl_or_b32 v14, v17, 16, v14
-; GFX12-NEXT:    v_lshl_or_b32 v15, v19, 16, v16
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_wmma_f16_16x16x16_f16 v[12:15], v[0:3], v[4:7], v[12:15] neg_lo:[0,0,1]
-; GFX12-NEXT:    global_store_b128 v[10:11], v[12:15], off
-; GFX12-NEXT:    s_endpgm
+; GFX1170-FAKE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX1170-FAKE16:       ; %bb.0: ; %bb
+; GFX1170-FAKE16-NEXT:    s_clause 0x1
+; GFX1170-FAKE16-NEXT:    flat_load_b128 v[12:15], v[8:9]
+; GFX1170-FAKE16-NEXT:    flat_load_b128 v[16:19], v[8:9] offset:16
+; GFX1170-FAKE16-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
+; GFX1170-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v12
+; GFX1170-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v14
+; GFX1170-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v16
+; GFX1170-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v18
+; GFX1170-FAKE16-NEXT:    v_lshl_or_b32 v12, v13, 16, v8
+; GFX1170-FAKE16-NEXT:    v_lshl_or_b32 v13, v15, 16, v9
+; GFX1170-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-FAKE16-NEXT:    v_lshl_or_b32 v14, v17, 16, v14
+; GFX1170-FAKE16-NEXT:    v_lshl_or_b32 v15, v19, 16, v16
+; GFX1170-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-FAKE16-NEXT:    v_wmma_f16_16x16x16_f16 v[12:15], v[0:3], v[4:7], v[12:15] neg_lo:[0,0,1]
+; GFX1170-FAKE16-NEXT:    global_store_b128 v[10:11], v[12:15], off
+; GFX1170-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX12-TRUE16:       ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    flat_load_b128 v[12:15], v[8:9]
+; GFX12-TRUE16-NEXT:    flat_load_b128 v[16:19], v[8:9] offset:16
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x101
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v15.l
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v17.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v18.h, v19.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v13.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v13, v14 :: v_dual_mov_b32 v14, v16
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v15, v18
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_wmma_f16_16x16x16_f16 v[12:15], v[0:3], v[4:7], v[12:15] neg_lo:[0,0,1]
+; GFX12-TRUE16-NEXT:    global_store_b128 v[10:11], v[12:15], off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX12-FAKE16:       ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    flat_load_b128 v[12:15], v[8:9]
+; GFX12-FAKE16-NEXT:    flat_load_b128 v[16:19], v[8:9] offset:16
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x101
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v12
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v14
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v16
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v18
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v12, v13, 16, v8
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v13, v15, 16, v9
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v14, v17, 16, v14
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v15, v19, 16, v16
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_wmma_f16_16x16x16_f16 v[12:15], v[0:3], v[4:7], v[12:15] neg_lo:[0,0,1]
+; GFX12-FAKE16-NEXT:    global_store_b128 v[10:11], v[12:15], off
+; GFX12-FAKE16-NEXT:    s_endpgm
 bb:
   %C = load <16 x half>, ptr %Caddr
   %C_shuffle = shufflevector <16 x half> %C, <16 x half> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -468,3 +508,6 @@ declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v2i32.v8f32(<2 x i32>
 declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v2i32.v8f32(<2 x i32>, <2 x i32>, <8 x float>)
 declare <8 x float> @llvm.amdgcn.swmmac.f32.16x16x32.f16.v8f16.v16f16.v8f32.i16(<8 x half>, <16 x half>, <8 x float>, i16)
 declare <8 x half> @llvm.amdgcn.swmmac.f16.16x16x32.f16.v8f16.v16f16.v8f16.i16(<8 x half>, <16 x half>, <8 x half>, i16)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1170: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
index 5839534a5dc78..2b84ad83aab50 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu11.70 -mattr=+wavefrontsize64,-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX1170
-; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=+wavefrontsize64,-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX12
+; RUN: llc -global-isel -mtriple=amdgpu11.70 -mattr=+wavefrontsize64,+real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX1170,GFX1170-TRUE16
+; RUN: llc -global-isel -mtriple=amdgpu11.70 -mattr=+wavefrontsize64,-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX1170,GFX1170-FAKE16
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=+wavefrontsize64,+real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX12,GFX12-TRUE16
+; RUN: llc -global-isel -mtriple=amdgpu12.00 -mattr=+wavefrontsize64,-real-true16 < %s | FileCheck %s --check-prefixes=GCN,GFX12,GFX12-FAKE16
 
 define amdgpu_ps void @test_wmma_f32_16x16x16_f16_negA(<4 x half> %A, <4 x half> %B, <4 x float> %C, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_wmma_f32_16x16x16_f16_negA:
@@ -367,33 +369,57 @@ bb:
 ; pack f16 elements with v_perm_b32 since they don't come from same b32
 
 define amdgpu_ps void @test_wmma_f16_16x16x16_f16_negC_pack(<4 x half> %A, <4 x half> %B, ptr %Caddr, ptr addrspace(1) %out) {
-; GFX1170-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
-; GFX1170:       ; %bb.0: ; %bb
-; GFX1170-NEXT:    flat_load_b128 v[8:11], v[4:5]
-; GFX1170-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX1170-NEXT:    v_and_b32_e32 v4, 0xffff, v8
-; GFX1170-NEXT:    v_and_b32_e32 v5, 0xffff, v10
-; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-NEXT:    v_lshl_or_b32 v4, v9, 16, v4
-; GFX1170-NEXT:    v_lshl_or_b32 v5, v11, 16, v5
-; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT:    v_wmma_f16_16x16x16_f16 v[4:5], v[0:1], v[2:3], v[4:5] neg_lo:[0,0,1]
-; GFX1170-NEXT:    global_store_b64 v[6:7], v[4:5], off
-; GFX1170-NEXT:    s_endpgm
+; GFX1170-TRUE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX1170-TRUE16:       ; %bb.0: ; %bb
+; GFX1170-TRUE16-NEXT:    flat_load_b128 v[8:11], v[4:5]
+; GFX1170-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v11.l
+; GFX1170-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v9.l
+; GFX1170-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT:    v_mov_b32_e32 v9, v10
+; GFX1170-TRUE16-NEXT:    v_wmma_f16_16x16x16_f16 v[8:9], v[0:1], v[2:3], v[8:9] neg_lo:[0,0,1]
+; GFX1170-TRUE16-NEXT:    global_store_b64 v[6:7], v[8:9], off
+; GFX1170-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
-; GFX12:       ; %bb.0: ; %bb
-; GFX12-NEXT:    flat_load_b128 v[8:11], v[4:5]
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v8
-; GFX12-NEXT:    v_and_b32_e32 v5, 0xffff, v10
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_lshl_or_b32 v4, v9, 16, v4
-; GFX12-NEXT:    v_lshl_or_b32 v5, v11, 16, v5
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_wmma_f16_16x16x16_f16 v[4:5], v[0:1], v[2:3], v[4:5] neg_lo:[0,0,1]
-; GFX12-NEXT:    global_store_b64 v[6:7], v[4:5], off
-; GFX12-NEXT:    s_endpgm
+; GFX1170-FAKE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX1170-FAKE16:       ; %bb.0: ; %bb
+; GFX1170-FAKE16-NEXT:    flat_load_b128 v[8:11], v[4:5]
+; GFX1170-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v8
+; GFX1170-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v10
+; GFX1170-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-FAKE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v4
+; GFX1170-FAKE16-NEXT:    v_lshl_or_b32 v5, v11, 16, v5
+; GFX1170-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-FAKE16-NEXT:    v_wmma_f16_16x16x16_f16 v[4:5], v[0:1], v[2:3], v[4:5] neg_lo:[0,0,1]
+; GFX1170-FAKE16-NEXT:    global_store_b64 v[6:7], v[4:5], off
+; GFX1170-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX12-TRUE16:       ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT:    flat_load_b128 v[8:11], v[4:5]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v11.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v9.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v10
+; GFX12-TRUE16-NEXT:    v_wmma_f16_16x16x16_f16 v[8:9], v[0:1], v[2:3], v[8:9] neg_lo:[0,0,1]
+; GFX12-TRUE16-NEXT:    global_store_b64 v[6:7], v[8:9], off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX12-FAKE16:       ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT:    flat_load_b128 v[8:11], v[4:5]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v8
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v10
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v4
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v5, v11, 16, v5
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_wmma_f16_16x16x16_f16 v[4:5], v[0:1], v[2:3], v[4:5] neg_lo:[0,0,1]
+; GFX12-FAKE16-NEXT:    global_store_b64 v[6:7], v[4:5], off
+; GFX12-FAKE16-NEXT:    s_endpgm
 bb:
   %C = load <8 x half>, ptr %Caddr
   %C_shuffle = shufflevector <8 x half> %C, <8 x half> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -416,3 +442,6 @@ declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.i32.v4f32(i32, i32, <
 declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.i32.v4f32(i32, i32, <4 x float>)
 declare <4 x float> @llvm.amdgcn.swmmac.f32.16x16x32.f16.v4f16.v8f16.v4f32.i16(<4 x half>, <8 x half>, <4 x float>, i16)
 declare <4 x half> @llvm.amdgcn.swmmac.f16.16x16x32.f16.v4f16.v8f16.v4f16.i16(<4 x half>, <8 x half>, <4 x half>, i16)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1170: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
index ae8b16d1a9479..93b446e6dcbf6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgpu11.70 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX1170 %s
-; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX12 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX12,GFX12-FAKE16 %s
 ; RUN: llc -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX1250,GFX1250-TRUE16 %s
 ; RUN: llc -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX1250,GFX1250-FAKE16 %s
 
@@ -105,13 +106,19 @@ define amdgpu_cs void @test_cvt_pk_bf8_f32_word0(i32 %a, float %y, i32 %old, ptr
 ; GFX1170-NEXT:    global_store_b32 v[3:4], v2, off
 ; GFX1170-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_cvt_pk_bf8_f32_word0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cvt_pk_bf8_f32 v2.l, v0, v1
-; GFX12-NEXT:    global_store_b32 v[3:4], v2, off
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: test_cvt_pk_bf8_f32_word0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_cvt_pk_bf8_f32 v2.l, v0, v1
+; GFX12-TRUE16-NEXT:    global_store_b32 v[3:4], v2, off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_cvt_pk_bf8_f32_word0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_cvt_pk_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX12-FAKE16-NEXT:    global_store_b32 v[3:4], v2, off
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-TRUE16-LABEL: test_cvt_pk_bf8_f32_word0:
 ; GFX1250-TRUE16:       ; %bb.0:
@@ -150,13 +157,21 @@ define amdgpu_cs void @test_cvt_pk_fp8_f32_word1(i32 %a, float %y, i32 %old, ptr
 ; GFX1170-NEXT:    global_store_b32 v[3:4], v2, off
 ; GFX1170-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_cvt_pk_fp8_f32_word1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cvt_pk_fp8_f32 v2.h, v0, v1
-; GFX12-NEXT:    global_store_b32 v[3:4], v2, off
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_cvt_pk_fp8_f32 v2.h, v0, v1
+; GFX12-TRUE16-NEXT:    global_store_b32 v[3:4], v2, off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_cvt_pk_fp8_f32_word1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1]
+; GFX12-FAKE16-NEXT:    global_store_b32 v[3:4], v2, off
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1:
 ; GFX1250-TRUE16:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
index 91a7e4937bdee..6f58dbbce3e77 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
 ; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI-SDAG %s
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
index 2ec91f678f85b..4876cd4c5f0a9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize32",+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize32",-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
 ; RUN: llc -mtriple=amdgpu10.10 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX10,SDAG-GFX10 %s
 
-; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize32",+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize32",-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
 ; RUN: llc -global-isel=1 -mtriple=amdgpu10.10 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX10,GISEL-GFX10 %s
 
 declare i32 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
index 4456597576b90..541a7c73e8c07 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
@@ -1,9 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
 ; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN,VI,SDAG-VI %s
 ; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX9,SDAG-GFX9 %s
 
-; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr="+wavefrontsize64",-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
 ; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN,VI,GISEL-VI %s
 ; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX9,GISEL-GFX9 %s
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
index 6f2a5774ed691..bdfe37fb28463 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
@@ -2,9 +2,12 @@
 ;RUN: llc < %s -mtriple=amdgpu6.01 | FileCheck %s --check-prefixes=PREGFX10,GFX6
 ;RUN: llc < %s -mtriple=amdgpu8.02 | FileCheck %s --check-prefixes=PREGFX10,GFX8
 ;RUN: llc < %s -mtriple=amdgpu10.10 | FileCheck %s --check-prefixes=GFX10
-;RUN: llc < %s -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX11
-;RUN: llc < %s -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX12,GFX12-SDAG
-;RUN: llc < %s -global-isel -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX12,GFX12-GISEL
+;RUN: llc < %s -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+real-true16 | FileCheck %s --check-prefixes=GFX11,GFX11-TRUE16
+;RUN: llc < %s -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=-real-true16 | FileCheck %s --check-prefixes=GFX11,GFX11-FAKE16
+;RUN: llc < %s -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -mattr=+real-true16 | FileCheck %s --check-prefixes=GFX12,GFX12-TRUE16,GFX12-SDAG-TRUE16
+;RUN: llc < %s -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -mattr=-real-true16 | FileCheck %s --check-prefixes=GFX12,GFX12-FAKE16,GFX12-SDAG-FAKE16
+;RUN: llc < %s -global-isel -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -mattr=+real-true16 | FileCheck %s --check-prefixes=GFX12,GFX12-TRUE16,GFX12-GISEL-TRUE16
+;RUN: llc < %s -global-isel -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -mattr=-real-true16 | FileCheck %s --check-prefixes=GFX12,GFX12-FAKE16,GFX12-GISEL-FAKE16
 
 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
 ; PREGFX10-LABEL: buffer_load:
@@ -634,39 +637,73 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32
 ; GFX11-NEXT:    exp mrt0, v4, v5, v0, v0 done
 ; GFX11-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: buffer_load_x1_offen_merged_or:
-; GFX12-SDAG:       ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT:    v_lshlrev_b32_e32 v4, 6, v0
-; GFX12-SDAG-NEXT:    s_clause 0x1
-; GFX12-SDAG-NEXT:    buffer_load_b128 v[0:3], v4, s[0:3], null offen offset:4
-; GFX12-SDAG-NEXT:    buffer_load_b64 v[4:5], v4, s[0:3], null offen offset:28
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x1
-; GFX12-SDAG-NEXT:    export mrt0, v0, v1, v2, v3 done
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    export mrt0, v4, v5, v0, v0 done
-; GFX12-SDAG-NEXT:    s_endpgm
-;
-; GFX12-GISEL-LABEL: buffer_load_x1_offen_merged_or:
-; GFX12-GISEL:       ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
-; GFX12-GISEL-NEXT:    v_or_b32_e32 v1, 4, v0
-; GFX12-GISEL-NEXT:    v_or_b32_e32 v2, 8, v0
-; GFX12-GISEL-NEXT:    v_or_b32_e32 v3, 12, v0
-; GFX12-GISEL-NEXT:    v_or_b32_e32 v4, 16, v0
-; GFX12-GISEL-NEXT:    v_or_b32_e32 v5, 28, v0
-; GFX12-GISEL-NEXT:    v_or_b32_e32 v0, 32, v0
-; GFX12-GISEL-NEXT:    s_clause 0x5
-; GFX12-GISEL-NEXT:    buffer_load_b32 v1, v1, s[0:3], null offen
-; GFX12-GISEL-NEXT:    buffer_load_b32 v2, v2, s[0:3], null offen
-; GFX12-GISEL-NEXT:    buffer_load_b32 v3, v3, s[0:3], null offen
-; GFX12-GISEL-NEXT:    buffer_load_b32 v4, v4, s[0:3], null offen
-; GFX12-GISEL-NEXT:    buffer_load_b32 v5, v5, s[0:3], null offen
-; GFX12-GISEL-NEXT:    buffer_load_b32 v0, v0, s[0:3], null offen
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x2
-; GFX12-GISEL-NEXT:    export mrt0, v1, v2, v3, v4 done
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    export mrt0, v5, v0, v0, v0 done
-; GFX12-GISEL-NEXT:    s_endpgm
+; GFX12-SDAG-TRUE16-LABEL: buffer_load_x1_offen_merged_or:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 6, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_clause 0x1
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_b128 v[0:3], v4, s[0:3], null offen offset:4
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_b64 v[4:5], v4, s[0:3], null offen offset:28
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-SDAG-TRUE16-NEXT:    export mrt0, v0, v1, v2, v3 done
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    export mrt0, v4, v5, v0, v0 done
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: buffer_load_x1_offen_merged_or:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 6, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_clause 0x1
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_b128 v[0:3], v4, s[0:3], null offen offset:4
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_b64 v[4:5], v4, s[0:3], null offen offset:28
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-SDAG-FAKE16-NEXT:    export mrt0, v0, v1, v2, v3 done
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    export mrt0, v4, v5, v0, v0 done
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-GISEL-TRUE16-LABEL: buffer_load_x1_offen_merged_or:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
+; GFX12-GISEL-TRUE16-NEXT:    v_or_b32_e32 v1, 4, v0
+; GFX12-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 8, v0
+; GFX12-GISEL-TRUE16-NEXT:    v_or_b32_e32 v3, 12, v0
+; GFX12-GISEL-TRUE16-NEXT:    v_or_b32_e32 v4, 16, v0
+; GFX12-GISEL-TRUE16-NEXT:    v_or_b32_e32 v5, 28, v0
+; GFX12-GISEL-TRUE16-NEXT:    v_or_b32_e32 v0, 32, v0
+; GFX12-GISEL-TRUE16-NEXT:    s_clause 0x5
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b32 v1, v1, s[0:3], null offen
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b32 v2, v2, s[0:3], null offen
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b32 v3, v3, s[0:3], null offen
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b32 v4, v4, s[0:3], null offen
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b32 v5, v5, s[0:3], null offen
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b32 v0, v0, s[0:3], null offen
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x2
+; GFX12-GISEL-TRUE16-NEXT:    export mrt0, v1, v2, v3, v4 done
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    export mrt0, v5, v0, v0, v0 done
+; GFX12-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-GISEL-FAKE16-LABEL: buffer_load_x1_offen_merged_or:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_or_b32_e32 v1, 4, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 8, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_or_b32_e32 v3, 12, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_or_b32_e32 v4, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_or_b32_e32 v5, 28, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_or_b32_e32 v0, 32, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_clause 0x5
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b32 v1, v1, s[0:3], null offen
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b32 v2, v2, s[0:3], null offen
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b32 v3, v3, s[0:3], null offen
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b32 v4, v4, s[0:3], null offen
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b32 v5, v5, s[0:3], null offen
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b32 v0, v0, s[0:3], null offen
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x2
+; GFX12-GISEL-FAKE16-NEXT:    export mrt0, v1, v2, v3, v4 done
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    export mrt0, v5, v0, v0, v0 done
+; GFX12-GISEL-FAKE16-NEXT:    s_endpgm
 main_body:
   %a = shl i32 %inp, 6
   %a1 = or i32 %a, 4
@@ -959,6 +996,63 @@ define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> in
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    ; return to shader part epilog
 ;
+; GFX12-SDAG-TRUE16-LABEL: buffer_load_int:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    s_clause 0x2
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_b64 v[4:5], off, s[0:3], null th:TH_LOAD_NT
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_b32 v6, off, s[0:3], null th:TH_LOAD_HT
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: buffer_load_int:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-FAKE16-NEXT:    s_clause 0x2
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_b64 v[4:5], off, s[0:3], null th:TH_LOAD_NT
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_b32 v6, off, s[0:3], null th:TH_LOAD_HT
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: buffer_load_int:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    s_clause 0x2
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b64 v[4:5], off, s[0:3], null th:TH_LOAD_NT
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_b32 v6, off, s[0:3], null th:TH_LOAD_HT
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x2
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: buffer_load_int:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-FAKE16-NEXT:    s_clause 0x2
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], null
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b64 v[4:5], off, s[0:3], null th:TH_LOAD_NT
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_b32 v6, off, s[0:3], null th:TH_LOAD_HT
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x2
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 ; GFX12-SDAG-LABEL: buffer_load_int:
 ; GFX12-SDAG:       ; %bb.0: ; %main_body
 ; GFX12-SDAG-NEXT:    s_clause 0x2
@@ -967,7 +1061,6 @@ define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> in
 ; GFX12-SDAG-NEXT:    buffer_load_b32 v6, off, s[0:3], null th:TH_LOAD_HT
 ; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
-;
 ; GFX12-GISEL-LABEL: buffer_load_int:
 ; GFX12-GISEL:       ; %bb.0: ; %main_body
 ; GFX12-GISEL-NEXT:    s_clause 0x2
@@ -1057,21 +1150,37 @@ define amdgpu_ps float @raw_buffer_load_i16(<4 x i32> inreg %rsrc) {
 ; GFX11-NEXT:    v_cvt_f32_u32_e32 v0, v0
 ; GFX11-NEXT:    ; return to shader part epilog
 ;
-; GFX12-SDAG-LABEL: raw_buffer_load_i16:
-; GFX12-SDAG:       ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT:    buffer_load_u16 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX12-SDAG-NEXT:    ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: raw_buffer_load_i16:
-; GFX12-GISEL:       ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT:    buffer_load_u16 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX12-GISEL-NEXT:    s_cvt_f32_u32 s0, s0
-; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: raw_buffer_load_i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_u16 v0, off, s[0:3], null
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: raw_buffer_load_i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_u16 v0, off, s[0:3], null
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: raw_buffer_load_i16:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_u16 v0, off, s[0:3], null
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-TRUE16-NEXT:    s_cvt_f32_u32 s0, s0
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: raw_buffer_load_i16:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_u16 v0, off, s[0:3], null
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_cvt_f32_u32 s0, s0
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
   %tmp2 = zext i16 %tmp to i32
@@ -1101,21 +1210,37 @@ define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) {
 ; GFX11-NEXT:    v_cvt_f32_i32_e32 v0, v0
 ; GFX11-NEXT:    ; return to shader part epilog
 ;
-; GFX12-SDAG-LABEL: raw_buffer_load_sbyte:
-; GFX12-SDAG:       ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT:    buffer_load_i8 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    v_cvt_f32_i32_e32 v0, v0
-; GFX12-SDAG-NEXT:    ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: raw_buffer_load_sbyte:
-; GFX12-GISEL:       ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT:    buffer_load_i8 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX12-GISEL-NEXT:    s_cvt_f32_i32 s0, s0
-; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: raw_buffer_load_sbyte:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_i8 v0, off, s[0:3], null
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: raw_buffer_load_sbyte:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_i8 v0, off, s[0:3], null
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: raw_buffer_load_sbyte:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_i8 v0, off, s[0:3], null
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-TRUE16-NEXT:    s_cvt_f32_i32 s0, s0
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: raw_buffer_load_sbyte:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_i8 v0, off, s[0:3], null
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_cvt_f32_i32 s0, s0
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
   %tmp2 = sext i8 %tmp to i32
@@ -1145,21 +1270,37 @@ define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) {
 ; GFX11-NEXT:    v_cvt_f32_i32_e32 v0, v0
 ; GFX11-NEXT:    ; return to shader part epilog
 ;
-; GFX12-SDAG-LABEL: raw_buffer_load_sshort:
-; GFX12-SDAG:       ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT:    buffer_load_i16 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    v_cvt_f32_i32_e32 v0, v0
-; GFX12-SDAG-NEXT:    ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: raw_buffer_load_sshort:
-; GFX12-GISEL:       ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT:    buffer_load_i16 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX12-GISEL-NEXT:    s_cvt_f32_i32 s0, s0
-; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: raw_buffer_load_sshort:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_i16 v0, off, s[0:3], null
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: raw_buffer_load_sshort:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-FAKE16-NEXT:    buffer_load_i16 v0, off, s[0:3], null
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: raw_buffer_load_sshort:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_i16 v0, off, s[0:3], null
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-TRUE16-NEXT:    s_cvt_f32_i32 s0, s0
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: raw_buffer_load_sshort:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-FAKE16-NEXT:    buffer_load_i16 v0, off, s[0:3], null
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_cvt_f32_i32 s0, s0
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
   %tmp2 = sext i16 %tmp to i32
@@ -1190,21 +1331,28 @@ define amdgpu_ps void @raw_buffer_load_f16(<4 x i32> inreg %rsrc, ptr addrspace(
 ; GFX11-NEXT:    ds_store_b16 v0, v1
 ; GFX11-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: raw_buffer_load_f16:
-; GFX12-SDAG:       ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT:    buffer_load_u16 v1, off, s[0:3], null
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    ds_store_b16 v0, v1
-; GFX12-SDAG-NEXT:    s_endpgm
-;
-; GFX12-GISEL-LABEL: raw_buffer_load_f16:
-; GFX12-GISEL:       ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT:    buffer_load_u16 v1, off, s[0:3], null
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX12-GISEL-NEXT:    v_mov_b16_e32 v1.l, s0
-; GFX12-GISEL-NEXT:    ds_store_b16 v0, v1
-; GFX12-GISEL-NEXT:    s_endpgm
+; GFX12-SDAG-TRUE16-LABEL: raw_buffer_load_f16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    buffer_load_u16 v1, off, s[0:3], null
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ds_store_b16 v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: raw_buffer_load_f16:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[0:3], null
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    ds_store_b16 v0, v1
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-GISEL-TRUE16-LABEL: raw_buffer_load_f16:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    buffer_load_u16 v1, off, s[0:3], null
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s0
+; GFX12-GISEL-TRUE16-NEXT:    ds_store_b16 v0, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_endpgm
 main_body:
   %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
   store half %val, ptr addrspace(3) %ptr
@@ -1547,3 +1695,7 @@ declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32) #0
 declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32) #0
 declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32) #0
 attributes #0 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-FAKE16: {{.*}}
+; GFX11-TRUE16: {{.*}}
+; GFX12-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index c5106d4fc0d66..7355ab59e1bbd 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -2,9 +2,10 @@
 ; RUN: llc -mtriple=amdgpu6.00-- < %s | FileCheck -check-prefix=GFX6 %s
 ; RUN: llc -mtriple=amdgpu8.02-- < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
-; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
 ; RUN: llc -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
-; RUN: llc -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
 
 define amdgpu_kernel void @constant_load_i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
 ; GFX6-LABEL: constant_load_i1:
@@ -153,15 +154,38 @@ define amdgpu_kernel void @constant_load_v2i1(ptr addrspace(1) %out, ptr addrspa
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_load_v2i1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_load_v2i1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_load_v2i1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_load_v2i1:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_load_v2i1:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -175,19 +199,6 @@ define amdgpu_kernel void @constant_load_v2i1(ptr addrspace(1) %out, ptr addrspa
 ; GFX1250-FAKE16-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_load_v2i1:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <2 x i1>, ptr addrspace(4) %in
   store <2 x i1> %load, ptr addrspace(1) %out
   ret void
@@ -249,15 +260,38 @@ define amdgpu_kernel void @constant_load_v3i1(ptr addrspace(1) %out, ptr addrspa
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_load_v3i1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_load_v3i1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_load_v3i1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_load_v3i1:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_load_v3i1:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -271,19 +305,6 @@ define amdgpu_kernel void @constant_load_v3i1(ptr addrspace(1) %out, ptr addrspa
 ; GFX1250-FAKE16-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_load_v3i1:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <3 x i1>, ptr addrspace(4) %in
   store <3 x i1> %load, ptr addrspace(1) %out
   ret void
@@ -346,15 +367,38 @@ define amdgpu_kernel void @constant_load_v4i1(ptr addrspace(1) %out, ptr addrspa
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_load_v4i1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_load_v4i1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_load_v4i1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_load_v4i1:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_load_v4i1:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -368,19 +412,6 @@ define amdgpu_kernel void @constant_load_v4i1(ptr addrspace(1) %out, ptr addrspa
 ; GFX1250-FAKE16-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_load_v4i1:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <4 x i1>, ptr addrspace(4) %in
   store <4 x i1> %load, ptr addrspace(1) %out
   ret void
@@ -443,15 +474,38 @@ define amdgpu_kernel void @constant_load_v8i1(ptr addrspace(1) %out, ptr addrspa
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_load_v8i1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_load_v8i1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_load_v8i1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_load_v8i1:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_load_v8i1:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -465,19 +519,6 @@ define amdgpu_kernel void @constant_load_v8i1(ptr addrspace(1) %out, ptr addrspa
 ; GFX1250-FAKE16-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_load_v8i1:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <8 x i1>, ptr addrspace(4) %in
   store <8 x i1> %load, ptr addrspace(1) %out
   ret void
@@ -540,15 +581,38 @@ define amdgpu_kernel void @constant_load_v16i1(ptr addrspace(1) %out, ptr addrsp
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_load_v16i1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_load_v16i1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_load_v16i1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_load_v16i1:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u16 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_load_v16i1:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -562,19 +626,6 @@ define amdgpu_kernel void @constant_load_v16i1(ptr addrspace(1) %out, ptr addrsp
 ; GFX1250-FAKE16-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_load_v16i1:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u16 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <16 x i1>, ptr addrspace(4) %in
   store <16 x i1> %load, ptr addrspace(1) %out
   ret void
@@ -1088,19 +1139,33 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i32(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v2i1_to_v2i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v2, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
-; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v2i1_to_v2i32:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v2, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
+; GFX12-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v2i1_to_v2i32:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v2, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
+; GFX12-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_zextload_v2i1_to_v2i32:
 ; GFX1250:       ; %bb.0:
@@ -1273,21 +1338,58 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(ptr addrspace(1) %out
 ; EG-NEXT:     ADD_INT * T3.X, PV.X, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v3i1_to_v3i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v3, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v1, v3, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 2, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 1, v1
-; GFX12-NEXT:    v_bfe_u32 v1, v1, 1, 1
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v3i1_to_v3i32:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v1, v3, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v1, v1, 1, 1
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-TRUE16-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v3i1_to_v3i32:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v3, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v1, v1, 1, 1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_zextload_v3i1_to_v3i32:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v3, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_and_b32 s4, s2, 1
+; GFX1250-TRUE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s2, s2, 0x10001
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s2
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX1250-TRUE16-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_zextload_v3i1_to_v3i32:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -1306,27 +1408,6 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(ptr addrspace(1) %out
 ; GFX1250-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
 ; GFX1250-FAKE16-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_zextload_v3i1_to_v3i32:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v3, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_and_b32 s4, s2, 1
-; GFX1250-REAL16-NEXT:    s_lshr_b32 s3, s3, 2
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s2, s2, 0x10001
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s2
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v2, s3
-; GFX1250-REAL16-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <3 x i1>, ptr addrspace(4) %in
   %ext = zext <3 x i1> %load to <3 x i32>
   store <3 x i32> %ext, ptr addrspace(1) %out
@@ -1493,21 +1574,58 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v4i1_to_v4i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v4, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v1, v4, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v3, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v0, 1, v1
-; GFX12-NEXT:    v_bfe_u32 v2, v1, 2, 1
-; GFX12-NEXT:    v_bfe_u32 v1, v1, 1, 1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 3, v3
-; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v4i1_to_v4i32:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v1, v4, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v1
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v2, v1, 2, 1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v1, v1, 1, 1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v4i1_to_v4i32:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v4, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v2, v1, 2, 1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v1, v1, 1, 1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_zextload_v4i1_to_v4i32:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v4, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_and_b32 s4, s2, 1
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s5, s2, 0x10002
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s2, s2, 0x10001
+; GFX1250-TRUE16-NEXT:    s_lshr_b32 s3, s3, 3
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s2
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, s3
+; GFX1250-TRUE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_zextload_v4i1_to_v4i32:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -1527,27 +1645,6 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(ptr addrspace(1) %out
 ; GFX1250-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 3, v3
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_zextload_v4i1_to_v4i32:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v4, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v4, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_and_b32 s4, s2, 1
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s5, s2, 0x10002
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s2, s2, 0x10001
-; GFX1250-REAL16-NEXT:    s_lshr_b32 s3, s3, 3
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s2
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, s3
-; GFX1250-REAL16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <4 x i1>, ptr addrspace(4) %in
   %ext = zext <4 x i1> %load to <4 x i32>
   store <4 x i32> %ext, ptr addrspace(1) %out
@@ -1750,32 +1847,88 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
 ; EG-NEXT:     ADD_INT * T8.X, PS, literal.x,
 ; EG-NEXT:    4(5.605194e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v8i1_to_v8i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v8, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v8, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX12-NEXT:    s_bfe_u32 s5, s2, 0x10005
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10003
-; GFX12-NEXT:    s_bfe_u32 s4, s2, 0x10001
-; GFX12-NEXT:    s_and_b32 s6, s2, 1
-; GFX12-NEXT:    s_bfe_u32 s7, s2, 0x10002
-; GFX12-NEXT:    s_bfe_u32 s2, s2, 0x10004
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 7, v0
-; GFX12-NEXT:    v_bfe_u32 v2, v0, 6, 1
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s4
-; GFX12-NEXT:    v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s3
-; GFX12-NEXT:    v_mov_b32_e32 v6, s7
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v8i1_to_v8i32:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v8, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s5, s2, 0x10005
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10003
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10001
+; GFX12-TRUE16-NEXT:    s_and_b32 s6, s2, 1
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s7, s2, 0x10002
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s2, s2, 0x10004
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 7, v0
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v2, v0, 6, 1
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s4
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v6, s7
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v8i1_to_v8i32:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v8, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s5, s2, 0x10005
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10003
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0x10001
+; GFX12-FAKE16-NEXT:    s_and_b32 s6, s2, 1
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s7, s2, 0x10002
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s2, s2, 0x10004
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 7, v0
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v2, v0, 6, 1
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s4
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v6, s7
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_zextload_v8i1_to_v8i32:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v8, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-TRUE16-NEXT:    s_and_b32 s5, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10003
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10001
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s6, s2, 0x10005
+; GFX1250-TRUE16-NEXT:    s_and_b32 s7, s2, 1
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s8, s2, 0x10002
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s2, s2, 0x10004
+; GFX1250-TRUE16-NEXT:    s_lshr_b32 s9, s5, 7
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s5, s5, 0x10006
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s6
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v2, s5
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v7, s3
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v4, s7 :: v_dual_mov_b32 v5, s4
+; GFX1250-TRUE16-NEXT:    s_clause 0x1
+; GFX1250-TRUE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
+; GFX1250-TRUE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_zextload_v8i1_to_v8i32:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -1804,35 +1957,6 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_zextload_v8i1_to_v8i32:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v8, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v8, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1250-REAL16-NEXT:    s_and_b32 s5, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s3, s2, 0x10003
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x10001
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s6, s2, 0x10005
-; GFX1250-REAL16-NEXT:    s_and_b32 s7, s2, 1
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s8, s2, 0x10002
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s2, s2, 0x10004
-; GFX1250-REAL16-NEXT:    s_lshr_b32 s9, s5, 7
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s5, s5, 0x10006
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s6
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v2, s5
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v7, s3
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v4, s7 :: v_dual_mov_b32 v5, s4
-; GFX1250-REAL16-NEXT:    s_clause 0x1
-; GFX1250-REAL16-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
-; GFX1250-REAL16-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <8 x i1>, ptr addrspace(4) %in
   %ext = zext <8 x i1> %load to <8 x i32>
   store <8 x i32> %ext, ptr addrspace(1) %out
@@ -2134,46 +2258,86 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
 ; EG-NEXT:     ADD_INT * T14.X, T11.X, literal.x,
 ; EG-NEXT:    12(1.681558e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v16i1_to_v16i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v16, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_b16 v0, v16, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX12-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX12-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX12-NEXT:    s_bfe_u32 s4, s2, 0x10003
-; GFX12-NEXT:    s_bfe_u32 s5, s2, 0x10001
-; GFX12-NEXT:    s_bfe_u32 s6, s2, 0x10007
-; GFX12-NEXT:    s_bfe_u32 s7, s2, 0x10009
-; GFX12-NEXT:    s_bfe_u32 s8, s2, 0x1000d
-; GFX12-NEXT:    s_and_b32 s9, s2, 1
-; GFX12-NEXT:    s_bfe_u32 s10, s2, 0x1000a
-; GFX12-NEXT:    s_bfe_u32 s2, s2, 0x1000c
-; GFX12-NEXT:    s_bfe_u32 s11, s3, 0x10005
-; GFX12-NEXT:    s_bfe_u32 s12, s3, 0x1000b
-; GFX12-NEXT:    s_lshr_b32 s13, s3, 15
-; GFX12-NEXT:    s_bfe_u32 s14, s3, 0x10002
-; GFX12-NEXT:    s_bfe_u32 s15, s3, 0x10006
-; GFX12-NEXT:    s_bfe_u32 s16, s3, 0x10004
-; GFX12-NEXT:    s_bfe_u32 s17, s3, 0x10008
-; GFX12-NEXT:    s_bfe_u32 s3, s3, 0x1000e
-; GFX12-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
-; GFX12-NEXT:    v_dual_mov_b32 v13, s5 :: v_dual_mov_b32 v2, s3
-; GFX12-NEXT:    v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v8, s16
-; GFX12-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
-; GFX12-NEXT:    v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v4, s17
-; GFX12-NEXT:    v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v10, s15
-; GFX12-NEXT:    v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s9
-; GFX12-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v14, s14
-; GFX12-NEXT:    s_clause 0x3
-; GFX12-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX12-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX12-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v16i1_to_v16i32:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v16, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v16, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10003
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s5, s2, 0x10001
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s6, s2, 0x10007
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s7, s2, 0x10009
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s8, s2, 0x1000d
+; GFX12-TRUE16-NEXT:    s_and_b32 s9, s2, 1
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s10, s2, 0x1000a
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s2, s2, 0x1000c
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s11, s3, 0x10005
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s12, s3, 0x1000b
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s13, s3, 15
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s14, s3, 0x10002
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s15, s3, 0x10006
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s16, s3, 0x10004
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s17, s3, 0x10008
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s3, 0x1000e
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v13, s5 :: v_dual_mov_b32 v2, s3
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v8, s16
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v4, s17
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v10, s15
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s9
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v14, s14
+; GFX12-TRUE16-NEXT:    s_clause 0x3
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v16i1_to_v16i32:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v16, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v16, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-FAKE16-NEXT:    s_and_b32 s6, 0xffff, s2
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10003
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0x10001
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s5, s2, 0x10007
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s7, s2, 0x10009
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s8, s2, 0x1000d
+; GFX12-FAKE16-NEXT:    s_and_b32 s9, s2, 1
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s10, s2, 0x1000a
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s2, s2, 0x1000c
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s11, s6, 0x10005
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s12, s6, 0x1000b
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s13, s6, 15
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s14, s6, 0x10002
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s15, s6, 0x10006
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s16, s6, 0x10004
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s17, s6, 0x10008
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s6, s6, 0x1000e
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v2, s6
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v8, s16
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v4, s17
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v10, s15
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, s9
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v14, s14
+; GFX12-FAKE16-NEXT:    s_clause 0x3
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_zextload_v16i1_to_v16i32:
 ; GFX1250:       ; %bb.0:
@@ -5419,24 +5583,66 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v2i1_to_v2i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mov_b32_e32 v3, v1
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v2i1_to_v2i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v2i1_to_v2i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v1, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_zextload_v2i1_to_v2i64:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_and_b32 s2, s2, 1
+; GFX1250-TRUE16-NEXT:    s_lshr_b32 s3, s3, 1
+; GFX1250-TRUE16-NEXT:    s_and_b32 s2, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
+; GFX1250-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_zextload_v2i1_to_v2i64:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -5457,29 +5663,6 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
 ; GFX1250-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_zextload_v2i1_to_v2i64:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_and_b32 s2, s2, 1
-; GFX1250-REAL16-NEXT:    s_lshr_b32 s3, s3, 1
-; GFX1250-REAL16-NEXT:    s_and_b32 s2, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX1250-REAL16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
-; GFX1250-REAL16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <2 x i1>, ptr addrspace(4) %in
   %ext = zext <2 x i1> %load to <2 x i64>
   store <2 x i64> %ext, ptr addrspace(1) %out
@@ -5548,22 +5731,39 @@ define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(ptr addrspace(1) %out
 ; EG-NEXT:     MOV * T1.W, T1.Z,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v2i1_to_v2i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v4, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v4, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 1, v0
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_bfe_i32 v2, v1, 0, 1
-; GFX12-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v2i1_to_v2i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v4, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 1, v0
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v2, v1, 0, 1
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-TRUE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v2i1_to_v2i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v4, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 1, v0
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v2, v1, 0, 1
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_sextload_v2i1_to_v2i64:
 ; GFX1250:       ; %bb.0:
@@ -5665,26 +5865,76 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
 ; EG-NEXT:     ADD_INT * T3.X, PV.X, literal.x,
 ; EG-NEXT:    4(5.605194e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v3i1_to_v3i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v5, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v5, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX12-NEXT:    v_bfe_u32 v2, v0, 1, 1
-; GFX12-NEXT:    v_dual_mov_b32 v3, v5 :: v_dual_and_b32 v0, 1, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 2, v1
-; GFX12-NEXT:    v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v2, 0xffff, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    global_store_b64 v5, v[4:5], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v5, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v3i1_to_v3i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v5, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v2, v0, 1, 1
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v3, v5 :: v_dual_and_b32 v0, 1, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 2, v1
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v2, 0xffff, v2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    global_store_b64 v5, v[4:5], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v5, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v3i1_to_v3i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v5, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v2, v0, 1, 1
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v3, v5 :: v_dual_and_b32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 2, v1
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    global_store_b64 v5, v[4:5], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v5, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_zextload_v3i1_to_v3i64:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10001
+; GFX1250-TRUE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX1250-TRUE16-NEXT:    s_and_b32 s2, s2, 1
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX1250-TRUE16-NEXT:    s_and_b32 s2, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v0, s3
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s4
+; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX1250-TRUE16-NEXT:    global_store_b64 v1, v[0:1], s[0:1] offset:16
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_zextload_v3i1_to_v3i64:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -5711,35 +5961,6 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
 ; GFX1250-FAKE16-NEXT:    global_store_b64 v5, v[4:5], s[0:1] offset:16
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v5, v[0:3], s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_zextload_v3i1_to_v3i64:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x10001
-; GFX1250-REAL16-NEXT:    s_lshr_b32 s3, s3, 2
-; GFX1250-REAL16-NEXT:    s_and_b32 s2, s2, 1
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX1250-REAL16-NEXT:    s_and_b32 s2, 0xffff, s2
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v0, s3
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s4
-; GFX1250-REAL16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v2, s3
-; GFX1250-REAL16-NEXT:    global_store_b64 v1, v[0:1], s[0:1] offset:16
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX1250-REAL16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <3 x i1>, ptr addrspace(4) %in
   %ext = zext <3 x i1> %load to <3 x i64>
   store <3 x i64> %ext, ptr addrspace(1) %out
@@ -5826,28 +6047,51 @@ define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(ptr addrspace(1) %out
 ; EG-NEXT:     MOV * T1.W, T1.Z,
 ; EG-NEXT:    4(5.605194e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v3i1_to_v3i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v6, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v6, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 2, v0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 1, v0
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_bfe_i32 v4, v1, 0, 1
-; GFX12-NEXT:    v_bfe_i32 v2, v2, 0, 1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    global_store_b64 v6, v[4:5], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v3i1_to_v3i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v6, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v6, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 2, v0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 1, v0
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v4, v1, 0, 1
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    global_store_b64 v6, v[4:5], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v3i1_to_v3i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v6, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v6, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 2, v0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 1, v0
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v4, v1, 0, 1
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    global_store_b64 v6, v[4:5], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_sextload_v3i1_to_v3i64:
 ; GFX1250:       ; %bb.0:
@@ -5959,35 +6203,93 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
 ; EG-NEXT:     ADD_INT * T3.X, PV.X, literal.x,
 ; EG-NEXT:    4(5.605194e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v4i1_to_v4i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mov_b32_e32 v3, v1
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10002
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 3, v0
-; GFX12-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX12-NEXT:    v_mov_b32_e32 v0, s3
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10001
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT:    s_and_b32 s2, s2, 1
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX12-NEXT:    s_and_b32 s2, 0xffff, s2
-; GFX12-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v0, s2
-; GFX12-NEXT:    v_mov_b32_e32 v2, s3
-; GFX12-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v4i1_to_v4i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10002
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 3, v0
+; GFX12-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, s3
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10001
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-TRUE16-NEXT:    s_and_b32 s2, s2, 1
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX12-TRUE16-NEXT:    s_and_b32 s2, 0xffff, s2
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v4i1_to_v4i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v1, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10002
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 3, v0
+; GFX12-FAKE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s3
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10001
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT:    s_and_b32 s2, s2, 1
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX12-FAKE16-NEXT:    s_and_b32 s2, 0xffff, s2
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_zextload_v4i1_to_v4i64:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10002
+; GFX1250-TRUE16-NEXT:    s_lshr_b32 s3, s3, 3
+; GFX1250-TRUE16-NEXT:    s_and_b32 s4, 0xffff, s4
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v0, s4
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10001
+; GFX1250-TRUE16-NEXT:    s_and_b32 s2, s2, 1
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s3
+; GFX1250-TRUE16-NEXT:    s_and_b32 s2, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:16
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
+; GFX1250-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_zextload_v4i1_to_v4i64:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -6019,34 +6321,6 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
 ; GFX1250-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_zextload_v4i1_to_v4i64:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x10002
-; GFX1250-REAL16-NEXT:    s_lshr_b32 s3, s3, 3
-; GFX1250-REAL16-NEXT:    s_and_b32 s4, 0xffff, s4
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v0, s4
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v2, s3
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s3, s2, 0x10001
-; GFX1250-REAL16-NEXT:    s_and_b32 s2, s2, 1
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s3
-; GFX1250-REAL16-NEXT:    s_and_b32 s2, 0xffff, s2
-; GFX1250-REAL16-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
-; GFX1250-REAL16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <4 x i1>, ptr addrspace(4) %in
   %ext = zext <4 x i1> %load to <4 x i64>
   store <4 x i64> %ext, ptr addrspace(1) %out
@@ -6143,32 +6417,59 @@ define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(ptr addrspace(1) %out
 ; EG-NEXT:     MOV * T2.W, T2.Z,
 ; EG-NEXT:    4(5.605194e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v4i1_to_v4i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v8, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v8, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 3, v0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 2, v0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 1, v0
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-NEXT:    v_bfe_i32 v6, v1, 0, 1
-; GFX12-NEXT:    v_bfe_i32 v4, v2, 0, 1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-NEXT:    v_bfe_i32 v2, v3, 0, 1
-; GFX12-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v7, 31, v6
-; GFX12-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v4i1_to_v4i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v8, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 3, v0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 1, v0
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v6, v1, 0, 1
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v4, v2, 0, 1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v2, v3, 0, 1
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v7, 31, v6
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v4i1_to_v4i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v8, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 3, v0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 1, v0
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v6, v1, 0, 1
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v4, v2, 0, 1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v2, v3, 0, 1
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v7, 31, v6
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_sextload_v4i1_to_v4i64:
 ; GFX1250:       ; %bb.0:
@@ -6327,35 +6628,65 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
 ; EG-NEXT:     ADD_INT * T12.X, T9.X, literal.x,
 ; EG-NEXT:    12(1.681558e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v8i1_to_v8i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mov_b32_e32 v7, v1
-; GFX12-NEXT:    v_mov_b32_e32 v9, v1
-; GFX12-NEXT:    v_mov_b32_e32 v11, v1
-; GFX12-NEXT:    v_mov_b32_e32 v13, v1
-; GFX12-NEXT:    v_mov_b32_e32 v15, v1
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v12, v1, s[2:3]
-; GFX12-NEXT:    v_mov_b32_e32 v3, v1
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v0, 0xffff, v12
-; GFX12-NEXT:    v_bfe_u32 v6, v12, 5, 1
-; GFX12-NEXT:    v_bfe_u32 v4, v12, 4, 1
-; GFX12-NEXT:    v_bfe_u32 v10, v12, 3, 1
-; GFX12-NEXT:    v_bfe_u32 v8, v12, 2, 1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 7, v0
-; GFX12-NEXT:    v_bfe_u32 v0, v0, 6, 1
-; GFX12-NEXT:    v_bfe_u32 v14, v12, 1, 1
-; GFX12-NEXT:    v_and_b32_e32 v12, 1, v12
-; GFX12-NEXT:    s_clause 0x3
-; GFX12-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX12-NEXT:    global_store_b128 v1, v[4:7], s[0:1] offset:32
-; GFX12-NEXT:    global_store_b128 v1, v[8:11], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v1, v[12:15], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v8i1_to_v8i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v7, v1
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v1
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v11, v1
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v13, v1
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v15, v1
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v12, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v0, 0xffff, v12
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v6, v12, 5, 1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v4, v12, 4, 1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v10, v12, 3, 1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v8, v12, 2, 1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 7, v0
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v0, v0, 6, 1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v14, v12, 1, 1
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v12, 1, v12
+; GFX12-TRUE16-NEXT:    s_clause 0x3
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:48
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[4:7], s[0:1] offset:32
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[8:11], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[12:15], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v8i1_to_v8i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v7, v1
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v9, v1
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v11, v1
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v13, v1
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v15, v1
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v12, v1, s[2:3]
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v0, 0xffff, v12
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v6, v12, 5, 1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v4, v12, 4, 1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v10, v12, 3, 1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v8, v12, 2, 1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 7, v0
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v0, v0, 6, 1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v14, v12, 1, 1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v12, 1, v12
+; GFX12-FAKE16-NEXT:    s_clause 0x3
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1] offset:48
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[4:7], s[0:1] offset:32
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[8:11], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[12:15], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_zextload_v8i1_to_v8i64:
 ; GFX1250:       ; %bb.0:
@@ -6549,48 +6880,91 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
 ; EG-NEXT:     MOV * T8.W, T8.Z,
 ; EG-NEXT:    12(1.681558e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v8i1_to_v8i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v16, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_u8 v0, v16, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mov_b32_e32 v9, s3
-; GFX12-NEXT:    s_lshr_b32 s2, s3, 6
-; GFX12-NEXT:    s_lshr_b32 s4, s3, 7
-; GFX12-NEXT:    s_lshr_b32 s6, s3, 4
-; GFX12-NEXT:    s_lshr_b32 s8, s3, 5
-; GFX12-NEXT:    s_lshr_b32 s10, s3, 2
-; GFX12-NEXT:    s_lshr_b32 s12, s3, 3
-; GFX12-NEXT:    s_lshr_b32 s14, s3, 1
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v0, s2
-; GFX12-NEXT:    v_bfe_i32 v12, v9, 0, 1
-; GFX12-NEXT:    s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-NEXT:    v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
-; GFX12-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
-; GFX12-NEXT:    s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX12-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
-; GFX12-NEXT:    v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
-; GFX12-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
-; GFX12-NEXT:    v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v14, s14
-; GFX12-NEXT:    v_ashrrev_i32_e32 v13, 31, v12
-; GFX12-NEXT:    v_mov_b32_e32 v15, s15
-; GFX12-NEXT:    s_clause 0x3
-; GFX12-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX12-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX12-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v8i1_to_v8i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v16, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v16, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, s3
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s2, s3, 6
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s4, s3, 7
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s6, s3, 4
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s8, s3, 5
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s10, s3, 2
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s12, s3, 3
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s14, s3, 1
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v12, v9, 0, 1
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v14, s14
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v13, 31, v12
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v15, s15
+; GFX12-TRUE16-NEXT:    s_clause 0x3
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v8i1_to_v8i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v16, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v16, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v9, s3
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s2, s3, 6
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s4, s3, 7
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s6, s3, 4
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s8, s3, 5
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s10, s3, 2
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s12, s3, 3
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s14, s3, 1
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v12, v9, 0, 1
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v14, s14
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v13, 31, v12
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v15, s15
+; GFX12-FAKE16-NEXT:    s_clause 0x3
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_sextload_v8i1_to_v8i64:
 ; GFX1250:       ; %bb.0:
@@ -6856,65 +7230,185 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
 ; EG-NEXT:     ADD_INT * T22.X, T15.X, literal.x,
 ; EG-NEXT:    28(3.923636e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v16i1_to_v16i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v3, 0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mov_b32_e32 v5, v3
-; GFX12-NEXT:    v_mov_b32_e32 v1, v3
-; GFX12-NEXT:    v_mov_b32_e32 v7, v3
-; GFX12-NEXT:    v_mov_b32_e32 v9, v3
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_b16 v0, v3, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX12-NEXT:    v_and_b32_e32 v6, 0xffff, v0
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x1000a
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_bfe_u32 v4, v6, 11, 1
-; GFX12-NEXT:    v_mov_b32_e32 v2, s3
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10009
-; GFX12-NEXT:    v_bfe_u32 v0, v6, 8, 1
-; GFX12-NEXT:    s_bfe_u32 s4, s2, 0x1000c
-; GFX12-NEXT:    v_lshrrev_b32_e32 v8, 15, v6
-; GFX12-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:80
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v2, s3
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x1000d
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v4, s3
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10007
-; GFX12-NEXT:    global_store_b128 v3, v[0:3], s[0:1] offset:64
-; GFX12-NEXT:    v_mov_b32_e32 v2, s4
-; GFX12-NEXT:    s_bfe_u32 s4, s2, 0x10006
-; GFX12-NEXT:    v_bfe_u32 v0, v6, 5, 1
-; GFX12-NEXT:    v_bfe_u32 v6, v6, 14, 1
-; GFX12-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:96
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v2, s4
-; GFX12-NEXT:    v_mov_b32_e32 v4, s3
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10004
-; GFX12-NEXT:    s_bfe_u32 s4, s2, 0x10002
-; GFX12-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:48
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v2, s3
-; GFX12-NEXT:    v_mov_b32_e32 v4, v0
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10003
-; GFX12-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:32
-; GFX12-NEXT:    v_mov_b32_e32 v2, s4
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v4, s3
-; GFX12-NEXT:    s_bfe_u32 s3, s2, 0x10001
-; GFX12-NEXT:    s_and_b32 s2, s2, 1
-; GFX12-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:16
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_mov_b32_e32 v2, s2
-; GFX12-NEXT:    v_mov_b32_e32 v4, s3
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    global_store_b128 v3, v[6:9], s[0:1] offset:112
-; GFX12-NEXT:    global_store_b128 v3, v[2:5], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v16i1_to_v16i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v5, v3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, v3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v7, v3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v3
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v3, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x1000a
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v4, v6, 11, 1
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10009
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v0, v6, 8, 1
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x1000c
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 15, v6
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:80
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x1000d
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10007
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[0:3], s[0:1] offset:64
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10006
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v0, v6, 5, 1
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v6, v6, 14, 1
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:96
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10004
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10002
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:48
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10003
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:32
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10001
+; GFX12-TRUE16-NEXT:    s_and_b32 s2, s2, 1
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s2
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[6:9], s[0:1] offset:112
+; GFX12-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v16i1_to_v16i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v5, v3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, v3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v7, v3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v9, v3
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v3, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x1000a
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v4, v6, 11, 1
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10009
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v0, v6, 8, 1
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0x1000c
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 15, v6
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:80
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x1000d
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10007
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[0:3], s[0:1] offset:64
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0x10006
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v0, v6, 5, 1
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v6, v6, 14, 1
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:96
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10004
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0x10002
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:48
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10003
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:32
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-FAKE16-NEXT:    s_bfe_u32 s3, s2, 0x10001
+; GFX12-FAKE16-NEXT:    s_and_b32 s2, s2, 1
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s2
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[6:9], s[0:1] offset:112
+; GFX12-FAKE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
+;
+; GFX1250-TRUE16-LABEL: constant_zextload_v16i1_to_v16i64:
+; GFX1250-TRUE16:       ; %bb.0:
+; GFX1250-TRUE16-NEXT:    global_wb
+; GFX1250-TRUE16-NEXT:    v_nop
+; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v1, v3
+; GFX1250-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT:    global_load_u16 v0, v3, s[2:3] nv
+; GFX1250-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-TRUE16-NEXT:    s_and_b32 s3, 0xffff, s2
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x1000a
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s5, s3, 0x1000b
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v2, s4
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v4, s5
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10009
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s5, s3, 0x10008
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:80
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v2, s5
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s5, s3, 0x1000e
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v4, s4
+; GFX1250-TRUE16-NEXT:    s_lshr_b32 s4, s3, 15
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s3, s3, 0x10005
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:64
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v2, s5
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s5, s2, 0x1000c
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v4, s4
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x1000d
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:112
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v2, s5
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s5, s2, 0x10006
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v4, s4
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10007
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:96
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10004
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:48
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s3, s2, 0x10003
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0x10002
+; GFX1250-TRUE16-NEXT:    s_bfe_u32 s2, s2, 0x10001
+; GFX1250-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:32
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:16
+; GFX1250-TRUE16-NEXT:    s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT:    v_mov_b32_e32 v2, s2
+; GFX1250-TRUE16-NEXT:    global_store_b128 v3, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-FAKE16-LABEL: constant_zextload_v16i1_to_v16i64:
 ; GFX1250-FAKE16:       ; %bb.0:
@@ -6961,66 +7455,6 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v1, v[24:27], s[0:1] offset:16
 ; GFX1250-FAKE16-NEXT:    global_store_b128 v1, v[28:31], s[0:1]
 ; GFX1250-FAKE16-NEXT:    s_endpgm
-;
-; GFX1250-REAL16-LABEL: constant_zextload_v16i1_to_v16i64:
-; GFX1250-REAL16:       ; %bb.0:
-; GFX1250-REAL16-NEXT:    global_wb
-; GFX1250-REAL16-NEXT:    v_nop
-; GFX1250-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1250-REAL16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v1, v3
-; GFX1250-REAL16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT:    global_load_u16 v0, v3, s[2:3] nv
-; GFX1250-REAL16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1250-REAL16-NEXT:    s_and_b32 s3, 0xffff, s2
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x1000a
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s5, s3, 0x1000b
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v2, s4
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v4, s5
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x10009
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s5, s3, 0x10008
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:80
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v2, s5
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s5, s3, 0x1000e
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v4, s4
-; GFX1250-REAL16-NEXT:    s_lshr_b32 s4, s3, 15
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s3, s3, 0x10005
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:64
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v2, s5
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s5, s2, 0x1000c
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v4, s4
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x1000d
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:112
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v2, s5
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s5, s2, 0x10006
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v4, s4
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x10007
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:96
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x10004
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:48
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s3, s2, 0x10003
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s4, s2, 0x10002
-; GFX1250-REAL16-NEXT:    s_bfe_u32 s2, s2, 0x10001
-; GFX1250-REAL16-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:32
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[2:5], s[0:1] offset:16
-; GFX1250-REAL16-NEXT:    s_wait_xcnt 0x0
-; GFX1250-REAL16-NEXT:    v_mov_b32_e32 v2, s2
-; GFX1250-REAL16-NEXT:    global_store_b128 v3, v[0:3], s[0:1]
-; GFX1250-REAL16-NEXT:    s_endpgm
   %load = load <16 x i1>, ptr addrspace(4) %in
   %ext = zext <16 x i1> %load to <16 x i64>
   store <16 x i64> %ext, ptr addrspace(1) %out
@@ -7303,77 +7737,149 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
 ; EG-NEXT:     MOV * T14.W, T14.Z,
 ; EG-NEXT:    28(3.923636e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v16i1_to_v16i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v32, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_d16_b16 v0, v32, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mov_b32_e32 v28, s3
-; GFX12-NEXT:    s_lshr_b32 s2, s3, 14
-; GFX12-NEXT:    s_lshr_b32 s4, s3, 15
-; GFX12-NEXT:    s_lshr_b32 s8, s3, 13
-; GFX12-NEXT:    s_lshr_b32 s10, s3, 10
-; GFX12-NEXT:    s_lshr_b32 s12, s3, 11
-; GFX12-NEXT:    s_lshr_b32 s6, s3, 12
-; GFX12-NEXT:    s_lshr_b32 s14, s3, 8
-; GFX12-NEXT:    s_lshr_b32 s16, s3, 9
-; GFX12-NEXT:    s_lshr_b32 s18, s3, 6
-; GFX12-NEXT:    s_lshr_b32 s20, s3, 7
-; GFX12-NEXT:    s_lshr_b32 s22, s3, 4
-; GFX12-NEXT:    s_lshr_b32 s24, s3, 5
-; GFX12-NEXT:    s_lshr_b32 s26, s3, 2
-; GFX12-NEXT:    s_lshr_b32 s28, s3, 3
-; GFX12-NEXT:    s_lshr_b32 s30, s3, 1
-; GFX12-NEXT:    s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s5
-; GFX12-NEXT:    v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
-; GFX12-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
-; GFX12-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v8, s10
-; GFX12-NEXT:    v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v10, s12
-; GFX12-NEXT:    v_mov_b32_e32 v13, s15
-; GFX12-NEXT:    v_bfe_i32 v28, v28, 0, 1
-; GFX12-NEXT:    s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX12-NEXT:    v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s9
-; GFX12-NEXT:    v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v15, s17
-; GFX12-NEXT:    v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v17, s19
-; GFX12-NEXT:    s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX12-NEXT:    s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX12-NEXT:    v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v19, s21
-; GFX12-NEXT:    v_dual_mov_b32 v18, s20 :: v_dual_mov_b32 v21, s23
-; GFX12-NEXT:    s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX12-NEXT:    v_dual_mov_b32 v20, s22 :: v_dual_mov_b32 v23, s25
-; GFX12-NEXT:    v_dual_mov_b32 v22, s24 :: v_dual_mov_b32 v25, s27
-; GFX12-NEXT:    v_dual_mov_b32 v24, s26 :: v_dual_mov_b32 v27, s29
-; GFX12-NEXT:    v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v31, s31
-; GFX12-NEXT:    v_mov_b32_e32 v30, s30
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    global_store_b128 v32, v[0:3], s[0:1] offset:112
-; GFX12-NEXT:    global_store_b128 v32, v[4:7], s[0:1] offset:96
-; GFX12-NEXT:    v_ashrrev_i32_e32 v29, 31, v28
-; GFX12-NEXT:    s_clause 0x5
-; GFX12-NEXT:    global_store_b128 v32, v[8:11], s[0:1] offset:80
-; GFX12-NEXT:    global_store_b128 v32, v[12:15], s[0:1] offset:64
-; GFX12-NEXT:    global_store_b128 v32, v[16:19], s[0:1] offset:48
-; GFX12-NEXT:    global_store_b128 v32, v[20:23], s[0:1] offset:32
-; GFX12-NEXT:    global_store_b128 v32, v[24:27], s[0:1] offset:16
-; GFX12-NEXT:    global_store_b128 v32, v[28:31], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v16i1_to_v16i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v32, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v32, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v28, s3
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s2, s3, 14
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s4, s3, 15
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s8, s3, 13
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s10, s3, 10
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s12, s3, 11
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s6, s3, 12
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s14, s3, 8
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s16, s3, 9
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s18, s3, 6
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s20, s3, 7
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s22, s3, 4
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s24, s3, 5
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s26, s3, 2
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s28, s3, 3
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s30, s3, 1
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s5
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v8, s10
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v10, s12
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v13, s15
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v28, v28, 0, 1
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s9
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v15, s17
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v17, s19
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v19, s21
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v18, s20 :: v_dual_mov_b32 v21, s23
+; GFX12-TRUE16-NEXT:    s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v20, s22 :: v_dual_mov_b32 v23, s25
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v22, s24 :: v_dual_mov_b32 v25, s27
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v24, s26 :: v_dual_mov_b32 v27, s29
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v31, s31
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v30, s30
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[0:3], s[0:1] offset:112
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[4:7], s[0:1] offset:96
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v29, 31, v28
+; GFX12-TRUE16-NEXT:    s_clause 0x5
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[8:11], s[0:1] offset:80
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[12:15], s[0:1] offset:64
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[16:19], s[0:1] offset:48
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[20:23], s[0:1] offset:32
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[24:27], s[0:1] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v32, v[28:31], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v16i1_to_v16i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v32, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v32, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v28, s3
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s2, s3, 14
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s4, s3, 15
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s8, s3, 13
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s10, s3, 10
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s12, s3, 11
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s6, s3, 12
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s14, s3, 8
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s16, s3, 9
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s18, s3, 6
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s20, s3, 7
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s22, s3, 4
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s24, s3, 5
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s26, s3, 2
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s28, s3, 3
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s30, s3, 1
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s5
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v8, s10
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v10, s12
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v13, s15
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v28, v28, 0, 1
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s9
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v15, s17
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v17, s19
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v19, s21
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v18, s20 :: v_dual_mov_b32 v21, s23
+; GFX12-FAKE16-NEXT:    s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v20, s22 :: v_dual_mov_b32 v23, s25
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v22, s24 :: v_dual_mov_b32 v25, s27
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v24, s26 :: v_dual_mov_b32 v27, s29
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v31, s31
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v30, s30
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[0:3], s[0:1] offset:112
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[4:7], s[0:1] offset:96
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v29, 31, v28
+; GFX12-FAKE16-NEXT:    s_clause 0x5
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[8:11], s[0:1] offset:80
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[12:15], s[0:1] offset:64
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[16:19], s[0:1] offset:48
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[20:23], s[0:1] offset:32
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[24:27], s[0:1] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v32, v[28:31], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-LABEL: constant_sextload_v16i1_to_v16i64:
 ; GFX1250:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/mul.ll b/llvm/test/CodeGen/AMDGPU/mul.ll
index 0f6a9317aa9d6..0b3d591358028 100644
--- a/llvm/test/CodeGen/AMDGPU/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul.ll
@@ -3,8 +3,10 @@
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX9 %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu10.10 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu11.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu12.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu11.00 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu11.00 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu12.00 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu12.00 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX12 %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu12.50 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX1250 %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgpu13.10 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX13 %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG %s
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
index bdba8aae77a71..8de7a0de592c7 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 ; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN-GISEL %s
 
 ; TODO: GlobalISel should avoid generating v_ldexp_f32.
@@ -57,10 +59,15 @@ define amdgpu_cs half @v_s_exp_f16(half inreg %src) {
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: v_s_exp_f16:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    v_exp_f16_e32 v0.l, s0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: v_s_exp_f16:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_exp_f16_e32 v0.l, s0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: v_s_exp_f16:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_exp_f16_e32 v0, s0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 ;
 ; GCN-GISEL-LABEL: v_s_exp_f16:
 ; GCN-GISEL:       ; %bb.0:
@@ -167,10 +174,15 @@ define amdgpu_cs half @v_s_log_f16(half inreg %src) {
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: v_s_log_f16:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    v_log_f16_e32 v0.l, s0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: v_s_log_f16:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, s0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: v_s_log_f16:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, s0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 ;
 ; GCN-GISEL-LABEL: v_s_log_f16:
 ; GCN-GISEL:       ; %bb.0:
@@ -215,16 +227,49 @@ define amdgpu_cs half @v_s_amdgcn_log_f16(half inreg %src) {
 }
 
 define void @v_amdgcn_log_f16_div(half %src, ptr addrspace(1) %out) {
-; GFX12-LABEL: v_amdgcn_log_f16_div:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_log_f16_e32 v0.l, v0.l
-; GFX12-NEXT:    global_store_b16 v[1:2], v0, off
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: v_amdgcn_log_f16_div:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: v_amdgcn_log_f16_div:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: v_amdgcn_log_f16_div:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: v_amdgcn_log_f16_div:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_amdgcn_log_f16_div:
 ; GCN-GISEL:       ; %bb.0:
@@ -297,16 +342,49 @@ define amdgpu_cs half @v_s_rcp_f16(half inreg %src) {
 }
 
 define void @v_rcp_f16_div(half %src, ptr addrspace(1) %out) {
-; GFX12-LABEL: v_rcp_f16_div:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_rcp_f16_e32 v0.l, v0.l
-; GFX12-NEXT:    global_store_b16 v[1:2], v0, off
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: v_rcp_f16_div:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: v_rcp_f16_div:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_rcp_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: v_rcp_f16_div:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: v_rcp_f16_div:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_rcp_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_rcp_f16_div:
 ; GCN-GISEL:       ; %bb.0:
@@ -713,10 +791,15 @@ define amdgpu_cs half @srcmods_abs_f16(half inreg %src) {
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: srcmods_abs_f16:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    v_log_f16_e64 v0.l, |s0|
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: srcmods_abs_f16:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, |s0|
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: srcmods_abs_f16:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, |s0|
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 ;
 ; GCN-GISEL-LABEL: srcmods_abs_f16:
 ; GCN-GISEL:       ; %bb.0:
@@ -736,10 +819,15 @@ define amdgpu_cs half @srcmods_neg_f16(half inreg %src) {
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: srcmods_neg_f16:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    v_log_f16_e64 v0.l, -s0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: srcmods_neg_f16:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, -s0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: srcmods_neg_f16:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, -s0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 ;
 ; GCN-GISEL-LABEL: srcmods_neg_f16:
 ; GCN-GISEL:       ; %bb.0:
@@ -774,26 +862,47 @@ define amdgpu_cs float @fdiv_f32_i32(float inreg %a, i32 inreg %b) {
 }
 
 define amdgpu_cs half @fdiv_f16_i16(half inreg %a, i16 inreg %b) {
-; GFX12-SDAG-LABEL: fdiv_f16_i16:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    v_cvt_f16_u16_e32 v0.l, s1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX12-SDAG-NEXT:    v_rcp_f16_e32 v0.l, v0.l
-; GFX12-SDAG-NEXT:    v_mul_f16_e32 v0.l, s0, v0.l
-; GFX12-SDAG-NEXT:    ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: fdiv_f16_i16:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    v_cvt_f16_u16_e32 v0.l, s1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_readfirstlane_b32 s1, v0
-; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT:    v_s_rcp_f16 s1, s1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
-; GFX12-GISEL-NEXT:    s_mul_f16 s0, s0, s1
-; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: fdiv_f16_i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.l, s1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, s0, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: fdiv_f16_i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    v_cvt_f16_u16_e32 v0, s1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_rcp_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, s0, v0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: fdiv_f16_i16:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.l, s1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-TRUE16-NEXT:    v_s_rcp_f16 s1, s1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-TRUE16-NEXT:    s_mul_f16 s0, s0, s1
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: fdiv_f16_i16:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_cvt_f16_u16_e32 v0, s1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-FAKE16-NEXT:    v_s_rcp_f16 s1, s1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-FAKE16-NEXT:    s_mul_f16 s0, s0, s1
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 ;
 ; GCN-GISEL-LABEL: fdiv_f16_i16:
 ; GCN-GISEL:       ; %bb.0:

