[llvm-branch-commits] [llvm] [AMDGPU] Refactor some existing test files with true16/fake16 split, add some new test cases (PR #209890)
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llvm-branch-commits at lists.llvm.org
Wed Jul 15 13:53:34 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Domenic Nutile (saxlungs)
<details>
<summary>Changes</summary>
PR stack:
https://github.com/llvm/llvm-project/pull/209891
https://github.com/llvm/llvm-project/pull/209890 <- YOU ARE HERE
https://github.com/llvm/llvm-project/pull/209889
https://github.com/llvm/llvm-project/pull/209888
<sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
---
Patch is 101.80 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209890.diff
9 Files Affected:
- (added) llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir (+102)
- (modified) llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir (+51-52)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll (+208-4)
- (modified) llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir (+192-192)
- (added) llvm/test/CodeGen/AMDGPU/shrink-fake16.mir (+55)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-true16.mir (+42-18)
- (added) llvm/test/CodeGen/AMDGPU/v_swap_b16.mir (+409)
- (added) llvm/test/CodeGen/AMDGPU/waitcnt-vinterp-fake16.mir (+30)
- (modified) llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir (+38-10)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir
new file mode 100644
index 0000000000000..ddf3aa2e17ca4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir
@@ -0,0 +1,102 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s
+
+---
+name: test_fmamk_reg_imm_f16
+registers:
+ - { id: 0, class: vreg_64 }
+ - { id: 1, class: vgpr_32 }
+ - { id: 2, class: vgpr_32 }
+ - { id: 3, class: vgpr_32 }
+ - { id: 4, class: vgpr_32 }
+body: |
+ bb.0:
+
+ ; GFX11-LABEL: name: test_fmamk_reg_imm_f16
+ ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
+ %0 = IMPLICIT_DEF
+ %1 = COPY %0.sub1
+ %2 = COPY %0.sub0
+ %3 = V_MOV_B32_e32 1078523331, implicit $exec
+ %4 = V_FMAC_F16_fake16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec
+
+...
+
+---
+name: test_fmamk_imm_reg_f16
+registers:
+ - { id: 0, class: vreg_64 }
+ - { id: 1, class: vgpr_32 }
+ - { id: 2, class: vgpr_32 }
+ - { id: 3, class: vgpr_32 }
+ - { id: 4, class: vgpr_32 }
+body: |
+ bb.0:
+
+ ; GFX11-LABEL: name: test_fmamk_imm_reg_f16
+ ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
+ %0 = IMPLICIT_DEF
+ %1 = COPY %0.sub1
+ %2 = COPY %0.sub0
+ %3 = V_MOV_B32_e32 1078523331, implicit $exec
+ %4 = V_FMAC_F16_fake16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec
+
+...
+
+---
+name: test_fmaak_f16
+registers:
+ - { id: 0, class: vreg_64 }
+ - { id: 1, class: vgpr_32 }
+ - { id: 2, class: vgpr_32 }
+ - { id: 3, class: vgpr_32 }
+ - { id: 4, class: vgpr_32 }
+body: |
+ bb.0:
+
+ ; GFX11-LABEL: name: test_fmaak_f16
+ ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec
+ %0 = IMPLICIT_DEF
+ %1 = COPY %0.sub0
+ %2 = COPY %0.sub1
+ %3 = V_MOV_B32_e32 1078523331, implicit $exec
+ %4 = V_FMAC_F16_fake16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, implicit $mode, implicit $exec
+...
+
+---
+name: test_fmaak_inline_literal_f16
+tracksRegLiveness: true
+liveins:
+ - { reg: '$vgpr0', virtual-reg: '%0' }
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GFX11-LABEL: name: test_fmaak_inline_literal_f16
+ ; GFX11: liveins: $vgpr0
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: S_ENDPGM 0
+ %0:vgpr_32 = COPY killed $vgpr0
+
+ %1:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
+ %2:vgpr_32 = V_FMAC_F16_fake16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, implicit $mode, implicit $exec
+ S_ENDPGM 0
+
+...
+
diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
index acea2e501283b..b4c9be4a2f928 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
@@ -1,86 +1,86 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s
-# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s
+# RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s
+# RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s
---
name: test_fmamk_reg_imm_f16
registers:
- - { id: 0, class: vreg_64 }
- - { id: 1, class: vgpr_32 }
- - { id: 2, class: vgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: vgpr_32 }
+ - { id: 0, class: vgpr_32 }
+ - { id: 1, class: vgpr_16 }
+ - { id: 2, class: vgpr_16 }
+ - { id: 3, class: vgpr_16 }
+ - { id: 4, class: vgpr_16 }
body: |
bb.0:
; GFX11-LABEL: name: test_fmamk_reg_imm_f16
- ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
- ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
- ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].hi16
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16
+ ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, killed [[COPY1]], 0, [[V_MOV_B16_t16_e64_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
%0 = IMPLICIT_DEF
- %1 = COPY %0.sub1
- %2 = COPY %0.sub0
- %3 = V_MOV_B32_e32 1078523331, implicit $exec
- %4 = V_FMAC_F16_fake16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec
+ %1 = COPY %0.hi16
+ %2 = COPY %0.lo16
+ %3 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec
+ %4 = V_FMAC_F16_t16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, 0, implicit $mode, implicit $exec
...
---
name: test_fmamk_imm_reg_f16
registers:
- - { id: 0, class: vreg_64 }
- - { id: 1, class: vgpr_32 }
- - { id: 2, class: vgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: vgpr_32 }
+ - { id: 0, class: vgpr_32 }
+ - { id: 1, class: vgpr_16 }
+ - { id: 2, class: vgpr_16 }
+ - { id: 3, class: vgpr_16 }
+ - { id: 4, class: vgpr_16 }
body: |
bb.0:
; GFX11-LABEL: name: test_fmamk_imm_reg_f16
- ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
- ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
- ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].hi16
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16
+ ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, [[COPY1]], 0, killed [[V_MOV_B16_t16_e64_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
%0 = IMPLICIT_DEF
- %1 = COPY %0.sub1
- %2 = COPY %0.sub0
- %3 = V_MOV_B32_e32 1078523331, implicit $exec
- %4 = V_FMAC_F16_fake16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec
+ %1 = COPY %0.hi16
+ %2 = COPY %0.lo16
+ %3 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec
+ %4 = V_FMAC_F16_t16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, 0, implicit $mode, implicit $exec
...
---
name: test_fmaak_f16
registers:
- - { id: 0, class: vreg_64 }
- - { id: 1, class: vgpr_32 }
- - { id: 2, class: vgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: vgpr_32 }
+ - { id: 0, class: vgpr_32 }
+ - { id: 1, class: vgpr_16 }
+ - { id: 2, class: vgpr_16 }
+ - { id: 3, class: vgpr_16 }
+ - { id: 4, class: vgpr_16 }
body: |
bb.0:
; GFX11-LABEL: name: test_fmaak_f16
- ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
- ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
- ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].hi16
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16
+ ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B16_t16_e64_]], 0, 0, 0, implicit $mode, implicit $exec
%0 = IMPLICIT_DEF
- %1 = COPY %0.sub0
- %2 = COPY %0.sub1
- %3 = V_MOV_B32_e32 1078523331, implicit $exec
- %4 = V_FMAC_F16_fake16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, implicit $mode, implicit $exec
+ %1 = COPY %0.hi16
+ %2 = COPY %0.lo16
+ %3 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec
+ %4 = V_FMAC_F16_t16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, 0, implicit $mode, implicit $exec
...
---
name: test_fmaak_inline_literal_f16
tracksRegLiveness: true
liveins:
- - { reg: '$vgpr0', virtual-reg: '%0' }
+ - { reg: '$vgpr0_hi16', virtual-reg: '%0' }
body: |
bb.0:
liveins: $vgpr0
@@ -88,14 +88,13 @@ body: |
; GFX11-LABEL: name: test_fmaak_inline_literal_f16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
- ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
- ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY killed $vgpr0_hi16
+ ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 999, 0, implicit $exec
+ ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B16_t16_e64_]], 0, 0, 0, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
- %0:vgpr_32 = COPY killed $vgpr0
-
- %1:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
- %2:vgpr_32 = V_FMAC_F16_fake16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, implicit $mode, implicit $exec
+ %0:vgpr_16 = COPY killed $vgpr0_hi16
+ %1:vgpr_16 = V_MOV_B16_t16_e64 0, 999, 0, implicit $exec
+ %2:vgpr_16 = V_FMAC_F16_t16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, 0, implicit $mode, implicit $exec
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
index baefe561e94ae..865cc0e61a919 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
@@ -1071,6 +1071,214 @@ define amdgpu_ps double @test_ldexp_f64_i32_uniform(double inreg %a, i32 inreg %
ret double %result
}
+define half @test_ldexp_f16_i32_neg(ptr addrspace(1) %out, half %a, i32 %b) {
+; GFX6-LABEL: test_ldexp_f16_i32_neg:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0, v3
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: test_ldexp_f16_i32_neg:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 0, v3
+; GFX8-NEXT: s_movk_i32 s4, 0x8000
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX8-NEXT: v_med3_i32 v0, v0, s4, v1
+; GFX8-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: test_ldexp_f16_i32_neg:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_sub_u32_e32 v0, 0, v3
+; GFX9-NEXT: s_movk_i32 s4, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
+; GFX9-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i32_neg:
+; GFX11-SDAG-TRUE16: ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3
+; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v0, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_ldexp_f16_i32_neg:
+; GFX11-SDAG-FAKE16: ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3
+; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v0, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i32_neg:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i32_neg:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3
+; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, v0, s0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %b.neg = sub i32 0, %b
+ %result = call half @llvm.ldexp.f16_i32(half %a, i32 %b.neg)
+ ret half %result
+}
+
+define half @ldexp_f16_i32_imm_a(ptr addrspace(1) %out, i32 %b) {
+; GFX6-LABEL: ldexp_f16_i32_imm_a:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_ldexp_f32_e32 v0, 2.0, v2
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-SDAG-LABEL: ldexp_f16_i32_imm_a:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_movk_i32 s4, 0x8000
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
+; GFX8-SDAG-NEXT: v_med3_i32 v0, v2, s4, v0
+; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-SDAG-LABEL: ldexp_f16_i32_imm_a:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff
+; GFX9-SDAG-NEXT: v_med3_i32 v0, v2, s4, v0
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: ldexp_f16_i32_imm_a:
+; GFX11-SDAG-TRUE16: ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v2, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, 2.0, v0.l
+; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: ldexp_f16_i32_imm_a:
+; GFX11-SDAG-FAKE16: ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v2, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
+; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: ldexp_f16_i32_imm_a:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0xffff8000
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX8-GISEL-NEXT: v_med3_i32 v0, v2, v0, v1
+; GFX8-GISEL-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: ldexp_f16_i32_imm_a:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v2, v0, v1
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: ldexp_f16_i32_imm_a:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, 2.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: ldexp_f16_i32_imm_a:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.ldexp.f16_i32(half 2.0, i32 %b)
+ ret half %result
+}
+
+define half @test_ldexp_f16_i32_imm_b(ptr addrspace(1) %out, half %a) {
+; GFX6-LABEL: test_ldexp_f16_i32_imm_b:...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/209890
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