[llvm-branch-commits] [llvm] [RISCV] Support CodeGen of Zilx extension (PR #209420)

[Pengcheng Wang via llvm-branch-commits]

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/209420

>From bf5ad3b324ff511ecc67ecf14c25cddabf9c7aa1 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Tue, 14 Jul 2026 17:56:49 +0800
Subject: [PATCH 1/2] clang-format

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9208762e8d1fe..0e69533f56a50 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3736,8 +3736,8 @@ static bool isRegRegScaleLoadOrStore(SDNode *User, SDValue Add,
     return false;
   EVT VT = cast<MemSDNode>(User)->getMemoryVT();
   if (!(VT.isScalarInteger() &&
-        (Subtarget.hasStdExtZilx() ||
-         Subtarget.hasVendorXTHeadMemIdx() || Subtarget.hasVendorXqcisls())) &&
+        (Subtarget.hasStdExtZilx() || Subtarget.hasVendorXTHeadMemIdx() ||
+         Subtarget.hasVendorXqcisls())) &&
       !((VT == MVT::f32 || VT == MVT::f64) &&
         Subtarget.hasVendorXTHeadFMemIdx()))
     return false;

>From ddc4fe1cd521bff676fcf361ab67acc72ad1671f Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 15 Jul 2026 14:49:45 +0800
Subject: [PATCH 2/2] Increase Complexity

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
index c7247efed0f4c..7c12cd63f99d0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
@@ -86,10 +86,11 @@ def LXD_S_UW  : IndexedLoad<0b101, 0b11, 0, "lxd.s.uw">,
 } // Predicates = [HasStdExtZilx, IsRV64]
 
 class AddrRegReg<int N>
-    : ComplexPattern<iPTR, 2, "SelectAddrRegRegFixedScale<"#N#">">;
+    : ComplexPattern<iPTR, 2, "SelectAddrRegRegFixedScale<"#N#">",
+                     [], [], !add(10, N)>;
 class AddrRegZextReg<int N>
     : ComplexPattern<i64, 2, "SelectAddrRegZextRegFixedScale<"#N#", 32>",
-                     [], [], 10>;
+                     [], [], !add(20, N)>;
 
 def AddrRegReg0 : AddrRegReg<0>;
 def AddrRegReg1 : AddrRegReg<1>;