[llvm-branch-commits] [llvm] [RISCV] Support CodeGen of Zilx extension (PR #209420)

[Sam Elliott via llvm-branch-commits]

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@@ -3736,7 +3736,8 @@ static bool isRegRegScaleLoadOrStore(SDNode *User, SDValue Add,
     return false;
   EVT VT = cast<MemSDNode>(User)->getMemoryVT();
   if (!(VT.isScalarInteger() &&
-        (Subtarget.hasVendorXTHeadMemIdx() || Subtarget.hasVendorXqcisls())) &&
+        (Subtarget.hasStdExtZilx() || Subtarget.hasVendorXTHeadMemIdx() ||
+         Subtarget.hasVendorXqcisls())) &&
       !((VT == MVT::f32 || VT == MVT::f64) &&
         Subtarget.hasVendorXTHeadFMemIdx()))
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lenary wrote:

Ok, fair enough.

I wondered if we could do something like `hasIndexLoadStore(MVT AccessTy, unsigned Shamt)` but I don't mind if the answer is still "no".

https://github.com/llvm/llvm-project/pull/209420