[llvm-branch-commits] [clang] [llvm] [X86][ACE] Add x86_bsr type and Block Scale Register support (PR #208706)

[via llvm-branch-commits]

mahesh-attarde wrote:

I understand use case where we use struct for bsr data, though it is not listed in spec.

I am not sure about concept of `no_bsr`, it is representing default bsr (0x7F)/OCP FP8 behavior.
I was thinking 
```

void test_scaled_top4mxhbf8ps(__acetile *dst, __m512i a, __m512i b, __m512i lo, __m512i hi) {
  __bsr scales = __bsr_make(lo, hi);
  __tile_ace_top4mxhbf8ps(dst, a, b, scales, 7);
}

#define __tile_ace_top4fp8ps(dst, src1, src2, scales, imm)               \
  (*(dst) = __builtin_ia32_top4mxhbf8ps_internal(                                  \
       16, 64, 64, (imm), *(dst), (__v16si)(src1), (__v16si)(src2),            \
       __bsr_default()

void test_ace_bsr_top4fp8ps(__acetile *dst, __m512i a, __m512i b, __m512i lo, __m512i hi) {
  __tile_ace_top4fp8ps(dst, a, b, 7);  
}

```
lets ideate on making it convenient for ACE programmers. 

* It would help if we can break down it into multiple issues, stacked-pr etc. something like
   + Enable bsr type
   + Enable intrinsics and isa
   + Enable dataflow
   + Optimize dataflow, diagnostics 
   + Enable spilling
  Ref: https://llvm.org/docs/GitHub.html#stacked-pull-requests

https://github.com/llvm/llvm-project/pull/208706