[llvm-branch-commits] [RISC-V][MC] Introduce initial support for RVY (CHERI) (PR #176871)

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git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp --diff_from_common_commit
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diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 57e6350b9..cbb9796f4 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -80,8 +80,8 @@ LLVMInitializeRISCVDisassembler() {
 
 template <unsigned BaseReg>
 static DecodeStatus decodeGPRLikeRC(MCInst &Inst, uint32_t RegNo,
-                                               uint64_t Address,
-                                               const MCDisassembler *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
 
   if (RegNo >= 32 || (IsRVE && RegNo >= 16))

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https://github.com/llvm/llvm-project/pull/176871