[llvm-branch-commits] [RISC-V][MC] Introduce initial support for RVY (CHERI) (PR #176871)

[Alexander Richardson via llvm-branch-commits]

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@@ -0,0 +1,108 @@
+//===-- RISCVInstrInfoY.td - RISCV instructions -------------*- tblgen-*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction Formats
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrFormatsY.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  class RVY_r<bits<5> funct5, string opcodestr, DAGOperand rdOp = GPR,
+              DAGOperand rs1Op = YGPR>
+      : RVYInstSrcDst<0x8, funct5, 0x0, OPC_OP, (outs rdOp:$rd),
+                      (ins rs1Op:$rs1), opcodestr, "$rd, $rs1">;
+  class RVY_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
+               DAGOperand rdOp = YGPR, DAGOperand rs1Op = YGPR,
+               DAGOperand rs2Op = GPR>
+      : RVInstR<funct7, funct3, OPC_OP, (outs rdOp:$rd),
+                (ins rs1Op:$rs1, rs2Op:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+  class RVY_ri<bits<3> funct3, RISCVOpcode opcode, string opcodestr,
+               DAGOperand rdOp = YGPR, DAGOperand rs1Op = YGPR>
+      : RVInstI<funct3, opcode, (outs rdOp:$rd),
+                (ins rs1Op:$rs1, simm12_lo:$imm12), opcodestr,
+                "$rd, $rs1, $imm12">;
+  class RVY_setboundsimm<string opcodestr>
+      : RVYInstSetBoundsImmFmt<(outs YGPR:$rd),
+                               (ins YGPR:$rs1, ybndsw_imm:$imm), opcodestr,
+                               "$rd, $rs1, $imm">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Predicates = [HasStdExtY] in {
+  //
+  // Instructions to Update The Capability Pointer
+  //
+  let isReMaterializable = true, isAsCheapAsAMove = true in {
+    def ADDY : RVY_rr<0x6, 0x0, "addy", YGPR, YGPR, GPRNoX0>;
+    def ADDIY : RVY_ri<0x2, OPC_OP_IMM_32, "addiy">;
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arichardson wrote:

I just looked at the generated table and it looks like we now check all instructions with some bit positions fixed first and the fall back to one with a wildcard. So if you mix P and Y you would get some P instructions in the disassembly stream. Is this okay for the initial version or should I mark P as conflicting?

https://github.com/llvm/llvm-project/pull/176871