[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

[Min-Yih Hsu via llvm-branch-commits]

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@@ -112,11 +168,58 @@ bool RISCVPreRAMachineSchedStrategy::tryCandidate(SchedCandidate &Cand,
 
     // Fall through to original instruction order.
     if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) ||
-        (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
+        (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum))
       TryCand.Reason = NodeOrder;
-      return true;
-    }
   }
 
-  return false;
+  //-------------------------------------------------------------------------//
+  // Below is RISC-V specific scheduling heuristics.
+  //-------------------------------------------------------------------------//
+
+  // Add RISC-V specific heuristic only when TryCand isn't selected or
+  // selected as node order.
+  if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
+    return true;
+
+  // TODO: We should not use `CandReason::Cluster` here, but is there a
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mshockwave wrote:

CandReason is only for diagnosing purposes, so this is probably fine. We can also add a `CandReason::Other` or `CandReason::Custom` in the future.

https://github.com/llvm/llvm-project/pull/95924