[llvm-branch-commits] [llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Gheorghe-Teodor Bercea via llvm-branch-commits]

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@@ -4550,6 +4550,35 @@ bool AMDGPUInstructionSelector::selectStackRestore(MachineInstr &MI) const {
   return true;
 }
 
+bool AMDGPUInstructionSelector::selectRegLoadStore(MachineInstr &I) const {
+  // Remember where the selected machine instruction will land.
+  MachineBasicBlock::iterator II = std::next(I.getIterator());
+
+  if (!selectImpl(I, *CoverageInfo))
+    return false;
+
+  // On a movrel subtarget the selected V_LOAD_IDX / V_STORE_IDX expands to an
+  // M0-relative move (see AMDGPUAssignIdxToM0 and expandVGPRIdxLoadStore). Add
+  // an implicit-def of $m0: it records that the eventual move clobbers M0, and
+  // - because an instruction defining a physical register is not hoisted/sunk -
+  // keeps a divergent access pinned inside its waterfall loop.
+  // AMDGPUAssignIdxToM0 removes it when it writes M0 for real.
+  if (!Subtarget->hasMovrel())
+    return true;
+
+  MachineInstr *Sel = &*std::prev(II);
+  if (SIInstrInfo::isVGPRIdxLoadStore(Sel->getOpcode())) {
+    // Record that this function performs a VGPR "as memory" access so
+    // AMDGPUAssignIdxToM0 can skip its scan otherwise.
+    Sel->getMF()->getInfo<SIMachineFunctionInfo>()->setHasVGPRAsMemoryAccess();
+    MachineOperand *Idx = TII.getNamedOperand(*Sel, AMDGPU::OpName::idx);
+    if (Idx && Idx->isReg())
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doru1004 wrote:

Also done

https://github.com/llvm/llvm-project/pull/209541