[llvm-branch-commits] [llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Matt Arsenault via llvm-branch-commits]

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@@ -0,0 +1,109 @@
+//===- AMDGPUAssignIdxToM0.cpp - Copy VGPR-memory indices to M0 ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
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arsenm wrote:

I don't really like this deferred insertion of required values. The required copies ought to be inserted during selection, and redundant cases optimized out later. That's how we handle other m0 writes, like pre-gfx9 LDS accesses. We have a special case optimization for this as it is, though this would be a lot easier if we stopped reserving m0. I think this kind of fixup pass, plus the fact that it's reserved, gives a buggy surface area for m0 liveness management 

https://github.com/llvm/llvm-project/pull/209541