[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: Detect address materialization and arithmetics (PR #132540)

[Kristof Beyls via llvm-branch-commits]

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@@ -304,6 +304,36 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
     }
   }
 
+  MCPhysReg getSafelyMaterializedAddressReg(const MCInst &Inst) const override {
+    switch (Inst.getOpcode()) {
+    case AArch64::ADR:
+    case AArch64::ADRP:
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kbeyls wrote:

Maybe there could be a comment here about why `ADR` and `ADRP` produce a "safely materialized address register"? For example, "These instructions produce an address value in the destination register, based only on information in parts of the instruction encoding, i.e. based on information from read-only code memory. Therefore, the value in the register it writes is safe according to the assumed threat model"

https://github.com/llvm/llvm-project/pull/132540