[llvm-branch-commits] [llvm] [AMDGPU] Precommit si-fold-bitmask.mir (PR #131310)

[Pierre van Houtryve via llvm-branch-commits]

Pierre-vh wrote:

> We can fold the clamp of the shift amount into the shift instruction during selection as we know the instruction ignores the high bits. We do that in the DAG path already. I think it special cases the and & (bitwidth - 1) pattern, which should form canonically. In principle it could do a general simplify demand bits

Where and how should that be implemented ? I struggled with that. I tried adding a new special case in TableGen but I just couldn't find the right way to do it.
Do I just add it in C++ InstructionSelector before it checks the patterns?
Or should it be some kind of post-processing step after the shift has been selected, but before the G_ZEXT is selected?


https://github.com/llvm/llvm-project/pull/131310