[llvm-branch-commits] [llvm] [AMDGPU] Precommit si-fold-bitmask.mir (PR #131310)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

> Then %2 being used as the shift amount. We can't eliminate the zext/trunc because the generic opcode has no mention of reading only the lower bits, AFAIK.

We can fold the clamp of the shift amount into the shift instruction during selection as we know the instruction ignores the high bits. We do that in the DAG path already. I think it special cases the and & (bitwidth - 1) pattern, which should form canonically. In principle it could do a general simplify demand bits 

https://github.com/llvm/llvm-project/pull/131310