[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Handle ISD::PTRADD in various special cases (PR #145330)

[Fabian Ritter via llvm-branch-commits]

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@@ -615,8 +615,14 @@ bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
       // operands on the new node are also disjoint.
       SDNodeFlags Flags(Op->getFlags().hasDisjoint() ? SDNodeFlags::Disjoint
                                                      : SDNodeFlags::None);
+      unsigned Opcode = Op.getOpcode();
+      if (Opcode == ISD::PTRADD) {
+        // It isn't a ptradd anymore if it doesn't operate on the entire
+        // pointer.
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ritter-x2a wrote:

You could make a PTRADD here work mechanically for AMDGPU by adding support of 32-bit PTRADDs (which requires more DAGCombines and is not on the critical path for me at the moment), but I'd still argue that this shouldn't be a PTRADD even then. As I see it, the point of having the PTRADD node is being able to tell that the left operand is an address, which it isn't if you chop off the leading bits (unless the chopping is done to implement an address space cast).

https://github.com/llvm/llvm-project/pull/145330