[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

[Min-Yih Hsu via llvm-branch-commits]

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@@ -13,19 +13,35 @@
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINESCHEDULER_H
 #define LLVM_LIB_TARGET_RISCV_RISCVMACHINESCHEDULER_H
 
+#include "RISCVSubtarget.h"
+#include "RISCVVSETVLIInfoAnalysis.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 
 namespace llvm {
 
 /// A GenericScheduler implementation for RISCV pre RA scheduling.
 class RISCVPreRAMachineSchedStrategy : public GenericScheduler {
+private:
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mshockwave wrote:

redundant `private`

https://github.com/llvm/llvm-project/pull/95924