[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

[Min-Yih Hsu via llvm-branch-commits]

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@@ -0,0 +1,677 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mcpu=spacemit-x60 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=DEFAULT
+; RUN: llc -mtriple=riscv64 -mcpu=spacemit-x60 -misched-prera-direction=bottomup \
+; RUN:   -riscv-enable-vtype-sched-heuristic -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=VTYPE-SCHED-BOTTOMUP
+; RUN: llc -mtriple=riscv64 -mcpu=spacemit-x60 -misched-prera-direction=topdown \
+; RUN:   -riscv-enable-vtype-sched-heuristic -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=VTYPE-SCHED-TOPDOWN
+; RUN: llc -mtriple=riscv64 -mcpu=spacemit-x60 -misched-prera-direction=bidirectional \
+; RUN:   -riscv-enable-vtype-sched-heuristic -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=VTYPE-SCHED-BIDIRECTIONAL
+
+define void @test(i16 %0, i16 %1, i16 %2, i16 %3, i16 %4, i16 %5, i16 %6, ptr %7, ptr %8, ptr %9, ptr %10, ptr %11, i32 %12) {
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mshockwave wrote:

recently Craig and I found that auto-generated scheduler tests are easier -- compared to normal codegen tests -- to overlook unintended / undesired changes upon updating through the UTC scripts. Is it possible to write this test manually, like checking the vsetvli instructions?

https://github.com/llvm/llvm-project/pull/95924