[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

[Min-Yih Hsu via llvm-branch-commits]

mshockwave wrote:

> This helps reduce register pressure for some cases.

Is it possible to provide some numbers to back this up? Preferably using some well known benchmarks like SPEC and/or llvm-test-suite

https://github.com/llvm/llvm-project/pull/115858