[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

[Michael Maitland via llvm-branch-commits]

michaelmaitland wrote:

For the recent scheduler patches, the common theme is we saw another target did something brought that functionality to RISC-V. How do we know that these changes are sensible defaults for RISC-V cores? Are you making measurements on any cores? Are they in order, out of order, both? In my experience tuning for different cores, there is often a difference between OOO and in order cores.

https://github.com/llvm/llvm-project/pull/115858