[llvm-branch-commits] [llvm] 74a60ee - [CodeGen][AArch64] Commit test for #65044

[Tobias Hieta via llvm-branch-commits]

Author: Danila Malyutin
Date: 2023-09-11T08:54:42+02:00
New Revision: 74a60ee0bbef1deb2b9a6c968790950027bb8e86

URL: https://github.com/llvm/llvm-project/commit/74a60ee0bbef1deb2b9a6c968790950027bb8e86
DIFF: https://github.com/llvm/llvm-project/commit/74a60ee0bbef1deb2b9a6c968790950027bb8e86.diff

LOG: [CodeGen][AArch64] Commit test for #65044

(cherry picked from commit 2fce8f74b3c04bbf7e941cfed7604edae2b573b6)

Added: 
    llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
new file mode 100644
index 000000000000000..e2216f9ece6b9f1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
@@ -0,0 +1,27 @@
+; XFAIL: *
+; RUN: llc %s --mattr=+complxnum -o - | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-ni:1-p2:32:8:8:32-ni:2"
+target triple = "aarch64-none-linux-gnu"
+
+; Check that deinterleaving pass doesn't generate broken IR
+define void @check_deinterleave_crash() #0 {
+bb:
+  br label %bb173
+
+bb173:                                            ; preds = %bb173, %bb
+  %phi177 = phi <2 x i32> [ %add190, %bb173 ], [ zeroinitializer, %bb ]
+  %phi178 = phi <2 x i32> [ %add187, %bb173 ], [ zeroinitializer, %bb ]
+  %add185 = add <2 x i32> %phi178, <i32 1, i32 1>
+  %add186 = add <2 x i32> %phi177, <i32 1, i32 1>
+  %shufflevector = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
+  %add187 = add <2 x i32> %add185, %shufflevector
+  %shufflevector189 = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
+  %add190 = add <2 x i32> %add186, %shufflevector189
+  br i1 poison, label %bb193, label %bb173
+
+bb193:                                            ; preds = %bb173
+  %add194 = or <2 x i32> %add190, %add187
+  store volatile i32 0, ptr null, align 4
+  unreachable
+}