[llvm-branch-commits] [clang] 80673e3 - [docs] Update the ACLE URL
Tobias Hieta via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Feb 20 00:34:35 PST 2023
Author: KAWASHIMA Takahiro
Date: 2023-02-20T09:32:53+01:00
New Revision: 80673e368452699b8e8a30f8c2b0c0ce23748228
URL: https://github.com/llvm/llvm-project/commit/80673e368452699b8e8a30f8c2b0c0ce23748228
DIFF: https://github.com/llvm/llvm-project/commit/80673e368452699b8e8a30f8c2b0c0ce23748228.diff
LOG: [docs] Update the ACLE URL
(cherry picked from commit e8d44841c5d5f1e7ca2013ab2ae23bb4cec45d1e)
Added:
Modified:
clang/docs/LanguageExtensions.rst
Removed:
################################################################################
diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst
index 1164efa63872..e5df4d524335 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -805,7 +805,7 @@ includes all 64-bit and all recent 32-bit processors.
``__fp16`` is a storage and interchange format only. This means that values of
``__fp16`` are immediately promoted to (at least) ``float`` when used in arithmetic
operations, so that e.g. the result of adding two ``__fp16`` values has type ``float``.
-The behavior of ``__fp16`` is specified by the ARM C Language Extensions (`ACLE <http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053d/IHI0053D_acle_2_1.pdf>`_).
+The behavior of ``__fp16`` is specified by the Arm C Language Extensions (`ACLE <https://github.com/ARM-software/acle/releases>`_).
Clang uses the ``binary16`` format from IEEE 754-2008 for ``__fp16``, not the ARM
alternative format.
@@ -3758,8 +3758,8 @@ ARM/AArch64 Language Extensions
Memory Barrier Intrinsics
^^^^^^^^^^^^^^^^^^^^^^^^^
Clang implements the ``__dmb``, ``__dsb`` and ``__isb`` intrinsics as defined
-in the `ARM C Language Extensions Release 2.0
-<http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf>`_.
+in the `Arm C Language Extensions
+<https://github.com/ARM-software/acle/releases>`_.
Note that these intrinsics are implemented as motion barriers that block
reordering of memory accesses and side effect instructions. Other instructions
like simple arithmetic may be reordered around the intrinsic. If you expect to
More information about the llvm-branch-commits
mailing list