[llvm-branch-commits] [llvm] f42a2ff - [DAGCombiner] Scalarize extend/truncate for splat vector.
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Jul 25 19:54:26 PDT 2022
Author: jacquesguan
Date: 2022-04-24T06:57:29Z
New Revision: f42a2ff321af8eadcee1e0436b4e6dc605081f93
URL: https://github.com/llvm/llvm-project/commit/f42a2ff321af8eadcee1e0436b4e6dc605081f93
DIFF: https://github.com/llvm/llvm-project/commit/f42a2ff321af8eadcee1e0436b4e6dc605081f93.diff
LOG: [DAGCombiner] Scalarize extend/truncate for splat vector.
This revision scalarizes extend/truncate for splat vector.
Differential Revision: https://reviews.llvm.org/D122875
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 71618eb2bd7c..ef269d346e82 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -434,6 +434,7 @@ namespace {
SDValue visitOR(SDNode *N);
SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
SDValue visitXOR(SDNode *N);
+ SDValue SimplifyVCastOp(SDNode *N, const SDLoc &DL);
SDValue SimplifyVBinOp(SDNode *N, const SDLoc &DL);
SDValue visitSHL(SDNode *N);
SDValue visitSRA(SDNode *N);
@@ -11812,6 +11813,10 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
EVT VT = N->getValueType(0);
SDLoc DL(N);
+ if (VT.isVector())
+ if (SDValue FoldedVOp = SimplifyVCastOp(N, DL))
+ return FoldedVOp;
+
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
return Res;
@@ -12057,6 +12062,10 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
+ if (VT.isVector())
+ if (SDValue FoldedVOp = SimplifyVCastOp(N, SDLoc(N)))
+ return FoldedVOp;
+
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
return Res;
@@ -15619,6 +15628,10 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
+ if (VT.isVector())
+ if (SDValue FoldedVOp = SimplifyVCastOp(N, SDLoc(N)))
+ return FoldedVOp;
+
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
if (N->hasOneUse() &&
N->use_begin()->getOpcode() == ISD::FP_ROUND)
@@ -23126,6 +23139,26 @@ static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG,
return DAG.getBuildVector(VT, DL, Ops);
}
+/// Visit a vector cast operation, like FP_EXTEND.
+SDValue DAGCombiner::SimplifyVCastOp(SDNode *N, const SDLoc &DL) {
+ EVT VT = N->getValueType(0);
+ assert(VT.isVector() && "SimplifyVCastOp only works on vectors!");
+ EVT EltVT = VT.getVectorElementType();
+
+ SDValue N0 = N->getOperand(0);
+ unsigned Opcode = N->getOpcode();
+
+ // TODO promote operation might be also good here?
+ if (N0.getOpcode() == ISD::SPLAT_VECTOR &&
+ TLI.isOperationLegalOrCustom(Opcode, EltVT)) {
+ SDValue Elt = N0.getOperand(0);
+ SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, Elt, N->getFlags());
+ return DAG.getSplatVector(VT, DL, ScalarBO);
+ }
+
+ return SDValue();
+}
+
/// Visit a binary vector operation, like ADD.
SDValue DAGCombiner::SimplifyVBinOp(SDNode *N, const SDLoc &DL) {
EVT VT = N->getValueType(0);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index ba2000e5a312..afc399cd704a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -413,15 +413,13 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
- vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
- def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
- (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
- vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+ vti.RegClass:$rs2, vti.RegClass:$rs1,
+ vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
- vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+ vti.RegClass:$rs2, vti.ScalarRegClass:$rs1,
+ vti.AVL, vti.Log2SEW)>;
}
}
@@ -432,15 +430,13 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
- wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
- def : Pat<(op (wti.Vector wti.RegClass:$rs2),
- (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
- (!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
- wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+ wti.RegClass:$rs2, vti.RegClass:$rs1,
+ vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
- wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+ wti.RegClass:$rs2, vti.ScalarRegClass:$rs1,
+ vti.AVL, vti.Log2SEW)>;
}
}
@@ -459,7 +455,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF<string instruction_name> {
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
- def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))),
+ def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
@@ -478,13 +474,13 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF<string instruction_name> {
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
- def : Pat<(fma (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))),
+ def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))),
(fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
- def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
+ def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
@@ -503,7 +499,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF<string instruction_name> {
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
- def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))),
+ def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
@@ -522,13 +518,13 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF<string instruction_name> {
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
- def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))),
+ def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))),
(fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
- def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
+ def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
index e020d2da7c28..f909fae27a42 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
@@ -604,11 +604,9 @@ define <vscale x 1 x float> @vfcopysign_exttrunc_vv_nxv1f32_nxv1f16(<vscale x 1
define <vscale x 1 x float> @vfcopysign_exttrunc_vf_nxv1f32_nxv1f16(<vscale x 1 x float> %vm, half %s) {
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f32_nxv1f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v10
+; CHECK-NEXT: fcvt.s.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vfsgnj.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -634,11 +632,9 @@ define <vscale x 1 x float> @vfcopynsign_exttrunc_vv_nxv1f32_nxv1f16(<vscale x 1
define <vscale x 1 x float> @vfcopynsign_exttrunc_vf_nxv1f32_nxv1f16(<vscale x 1 x float> %vm, half %s) {
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f32_nxv1f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
+; CHECK-NEXT: fcvt.s.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -866,11 +862,9 @@ define <vscale x 8 x float> @vfcopysign_exttrunc_vv_nxv8f32_nxv8f16(<vscale x 8
define <vscale x 8 x float> @vfcopysign_exttrunc_vf_nxv8f32_nxv8f16(<vscale x 8 x float> %vm, half %s) {
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v16, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v16
+; CHECK-NEXT: fcvt.s.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfsgnj.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -896,11 +890,9 @@ define <vscale x 8 x float> @vfcopynsign_exttrunc_vv_nxv8f32_nxv8f16(<vscale x 8
define <vscale x 8 x float> @vfcopynsign_exttrunc_vf_nxv8f32_nxv8f16(<vscale x 8 x float> %vm, half %s) {
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v16, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v16
+; CHECK-NEXT: fcvt.s.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -1082,13 +1074,9 @@ define <vscale x 1 x double> @vfcopysign_exttrunc_vv_nxv1f64_nxv1f16(<vscale x 1
define <vscale x 1 x double> @vfcopysign_exttrunc_vf_nxv1f64_nxv1f16(<vscale x 1 x double> %vm, half %s) {
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f64_nxv1f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v9
+; CHECK-NEXT: fcvt.d.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vfsgnj.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -1116,13 +1104,9 @@ define <vscale x 1 x double> @vfcopynsign_exttrunc_vv_nxv1f64_nxv1f16(<vscale x
define <vscale x 1 x double> @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f16(<vscale x 1 x double> %vm, half %s) {
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f64_nxv1f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
+; CHECK-NEXT: fcvt.d.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -1148,11 +1132,9 @@ define <vscale x 1 x double> @vfcopysign_exttrunc_vv_nxv1f64_nxv1f32(<vscale x 1
define <vscale x 1 x double> @vfcopysign_exttrunc_vf_nxv1f64_nxv1f32(<vscale x 1 x double> %vm, float %s) {
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f64_nxv1f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v10
+; CHECK-NEXT: fcvt.d.s ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vfsgnj.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> poison, float %s, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
@@ -1178,11 +1160,9 @@ define <vscale x 1 x double> @vfcopynsign_exttrunc_vv_nxv1f64_nxv1f32(<vscale x
define <vscale x 1 x double> @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f32(<vscale x 1 x double> %vm, float %s) {
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f64_nxv1f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
+; CHECK-NEXT: fcvt.d.s ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> poison, float %s, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
@@ -1354,13 +1334,9 @@ define <vscale x 8 x double> @vfcopysign_exttrunc_vv_nxv8f64_nxv8f16(<vscale x 8
define <vscale x 8 x double> @vfcopysign_exttrunc_vf_nxv8f64_nxv8f16(<vscale x 8 x double> %vm, half %s) {
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v20, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v24, v20
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v24
+; CHECK-NEXT: fcvt.d.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vfsgnj.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -1388,13 +1364,9 @@ define <vscale x 8 x double> @vfcopynsign_exttrunc_vv_nxv8f64_nxv8f16(<vscale x
define <vscale x 8 x double> @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f16(<vscale x 8 x double> %vm, half %s) {
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v20, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v24, v20
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v24
+; CHECK-NEXT: fcvt.d.h ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -1420,11 +1392,9 @@ define <vscale x 8 x double> @vfcopysign_exttrunc_vv_nxv8f64_nxv8f32(<vscale x 8
define <vscale x 8 x double> @vfcopysign_exttrunc_vf_nxv8f64_nxv8f32(<vscale x 8 x double> %vm, float %s) {
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f64_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v24, v16
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v24
+; CHECK-NEXT: fcvt.d.s ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vfsgnj.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %s, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
@@ -1450,11 +1420,9 @@ define <vscale x 8 x double> @vfcopynsign_exttrunc_vv_nxv8f64_nxv8f32(<vscale x
define <vscale x 8 x double> @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f32(<vscale x 8 x double> %vm, float %s) {
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f64_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v24, v16
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v24
+; CHECK-NEXT: fcvt.d.s ft0, fa0
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %s, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
index ad504c4c1614..11f4b7b6d423 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
@@ -17,11 +17,20 @@ define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale
}
define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv1i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsra.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv1i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vnsra.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv1i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsra.vx v8, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -58,12 +67,21 @@ define <vscale x 2 x i32> @vnsra_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale
}
define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv2i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v10, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv2i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vnsra.wx v10, v8, a0
+; RV32-NEXT: vmv.v.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv2i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsra.vx v10, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -101,12 +119,21 @@ define <vscale x 4 x i32> @vnsra_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale
}
define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv4i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v12, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv4i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vnsra.wx v12, v8, a0
+; RV32-NEXT: vmv.v.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv4i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsra.vx v12, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -144,12 +171,21 @@ define <vscale x 8 x i32> @vnsra_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale
}
define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv8i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v16, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv8i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vnsra.wx v16, v8, a0
+; RV32-NEXT: vmv.v.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv8i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsra.vx v16, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
@@ -186,11 +222,21 @@ define <vscale x 1 x i32> @vnsra_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale
}
define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv1i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsra.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv1i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vnsra.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv1i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsra.vx v8, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -227,12 +273,22 @@ define <vscale x 2 x i32> @vnsra_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale
}
define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv2i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v10, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv2i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vnsra.wx v10, v8, a0
+; RV32-NEXT: vmv.v.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv2i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsra.vx v10, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -270,12 +326,22 @@ define <vscale x 4 x i32> @vnsra_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale
}
define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv4i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v12, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv4i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vnsra.wx v12, v8, a0
+; RV32-NEXT: vmv.v.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv4i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsra.vx v12, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -313,12 +379,22 @@ define <vscale x 8 x i32> @vnsra_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale
}
define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv8i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v16, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsra_wx_i32_nxv8i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vnsra.wx v16, v8, a0
+; RV32-NEXT: vmv.v.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv8i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsra.vx v16, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
index 80e078f0b824..018787af7ac4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
@@ -17,11 +17,20 @@ define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale
}
define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv1i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vnsrl.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv1i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsrl.vx v8, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -58,12 +67,21 @@ define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale
}
define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v10, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv2i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vnsrl.wx v10, v8, a0
+; RV32-NEXT: vmv.v.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv2i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsrl.vx v10, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -101,12 +119,21 @@ define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale
}
define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v12, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv4i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vnsrl.wx v12, v8, a0
+; RV32-NEXT: vmv.v.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv4i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsrl.vx v12, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -144,12 +171,21 @@ define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale
}
define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_sext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v16, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv8i32_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vnsrl.wx v16, v8, a0
+; RV32-NEXT: vmv.v.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv8i32_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
@@ -186,11 +222,21 @@ define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale
}
define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv1i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vnsrl.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv1i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsrl.vx v8, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v8
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -227,12 +273,22 @@ define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale
}
define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v10, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv2i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vnsrl.wx v10, v8, a0
+; RV32-NEXT: vmv.v.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv2i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsrl.vx v10, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -270,12 +326,22 @@ define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale
}
define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v12, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv4i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vnsrl.wx v12, v8, a0
+; RV32-NEXT: vmv.v.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv4i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsrl.vx v12, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -313,12 +379,22 @@ define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale
}
define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_zext:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v16, v8, a0
-; CHECK-NEXT: vmv.v.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vnsrl_wx_i32_nxv8i32_zext:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vnsrl.wx v16, v8, a0
+; RV32-NEXT: vmv.v.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv8i32_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT: vncvt.x.x.w v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
index f538817e8772..c657ed71e546 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i64> @vwadd_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwadd_vv_nxv1i64:
@@ -29,12 +29,20 @@ define <vscale x 1 x i64> @vwaddu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1
}
define <vscale x 1 x i64> @vwadd_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.vx v9, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_vx_nxv1i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwadd.vx v9, v8, a0
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_vx_nxv1i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsext.vf2 v9, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vadd.vx v8, v9, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -44,12 +52,21 @@ define <vscale x 1 x i64> @vwadd_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
}
define <vscale x 1 x i64> @vwaddu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vx v9, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_vx_nxv1i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwaddu.vx v9, v8, a0
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_vx_nxv1i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vzext.vf2 v9, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vadd.vx v8, v9, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -83,11 +100,18 @@ define <vscale x 1 x i64> @vwaddu_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
}
define <vscale x 1 x i64> @vwadd_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_wx_nxv1i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwadd.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_wx_nxv1i64:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -96,11 +120,19 @@ define <vscale x 1 x i64> @vwadd_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
}
define <vscale x 1 x i64> @vwaddu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_wx_nxv1i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwaddu.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_wx_nxv1i64:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -135,12 +167,20 @@ define <vscale x 2 x i64> @vwaddu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2
}
define <vscale x 2 x i64> @vwadd_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.vx v10, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_vx_nxv2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwadd.vx v10, v8, a0
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_vx_nxv2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsext.vf2 v10, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vadd.vx v8, v10, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -150,12 +190,21 @@ define <vscale x 2 x i64> @vwadd_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
}
define <vscale x 2 x i64> @vwaddu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.vx v10, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_vx_nxv2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwaddu.vx v10, v8, a0
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_vx_nxv2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vzext.vf2 v10, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vadd.vx v8, v10, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -189,11 +238,18 @@ define <vscale x 2 x i64> @vwaddu_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
}
define <vscale x 2 x i64> @vwadd_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_wx_nxv2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwadd.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_wx_nxv2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -202,11 +258,19 @@ define <vscale x 2 x i64> @vwadd_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
}
define <vscale x 2 x i64> @vwaddu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_wx_nxv2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwaddu.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_wx_nxv2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -241,12 +305,20 @@ define <vscale x 4 x i64> @vwaddu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4
}
define <vscale x 4 x i64> @vwadd_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.vx v12, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_vx_nxv4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwadd.vx v12, v8, a0
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_vx_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vadd.vx v8, v12, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -256,12 +328,21 @@ define <vscale x 4 x i64> @vwadd_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
}
define <vscale x 4 x i64> @vwaddu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.vx v12, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_vx_nxv4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwaddu.vx v12, v8, a0
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_vx_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vzext.vf2 v12, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vadd.vx v8, v12, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -295,11 +376,18 @@ define <vscale x 4 x i64> @vwaddu_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
}
define <vscale x 4 x i64> @vwadd_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_wx_nxv4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwadd.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_wx_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -308,11 +396,19 @@ define <vscale x 4 x i64> @vwadd_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
}
define <vscale x 4 x i64> @vwaddu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_wx_nxv4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwaddu.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_wx_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -347,12 +443,20 @@ define <vscale x 8 x i64> @vwaddu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8
}
define <vscale x 8 x i64> @vwadd_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwadd.vx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwadd.vx v16, v8, a0
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vadd.vx v8, v16, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -362,12 +466,21 @@ define <vscale x 8 x i64> @vwadd_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
}
define <vscale x 8 x i64> @vwaddu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwaddu.vx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwaddu.vx v16, v8, a0
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vzext.vf2 v16, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vadd.vx v8, v16, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -401,11 +514,18 @@ define <vscale x 8 x i64> @vwaddu_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
}
define <vscale x 8 x i64> @vwadd_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwadd.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwadd_wx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwadd.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwadd_wx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
@@ -414,11 +534,19 @@ define <vscale x 8 x i64> @vwadd_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
}
define <vscale x 8 x i64> @vwaddu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwaddu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: vwaddu_wx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwaddu.wx v8, v8, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwaddu_wx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
index 2e373799ffe5..1c6e7e6c131f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmacc_vv_nxv1i32:
@@ -20,12 +20,21 @@ define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
}
define <vscale x 1 x i64> @vwmacc_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv1i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwmacc.vx v9, a0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmacc_vx_nxv1i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwmacc.vx v9, a0, v8
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmacc_vx_nxv1i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsext.vf2 v10, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v10, a0, v9
+; RV64-NEXT: vmv.v.v v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -52,12 +61,22 @@ define <vscale x 1 x i64> @vwmaccu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x
}
define <vscale x 1 x i64> @vwmaccu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv1i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwmaccu.vx v9, a0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccu_vx_nxv1i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwmaccu.vx v9, a0, v8
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv1i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vzext.vf2 v10, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v10, a0, v9
+; RV64-NEXT: vmv.v.v v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -84,12 +103,21 @@ define <vscale x 1 x i64> @vwmaccsu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x
}
define <vscale x 1 x i64> @vwmaccsu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv1i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwmaccsu.vx v9, a0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccsu_vx_nxv1i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwmaccsu.vx v9, a0, v8
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv1i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vzext.vf2 v10, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v10, a0, v9
+; RV64-NEXT: vmv.v.v v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -101,12 +129,22 @@ define <vscale x 1 x i64> @vwmaccsu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <
}
define <vscale x 1 x i64> @vwmaccus_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv1i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwmaccus.vx v9, a0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccus_vx_nxv1i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwmaccus.vx v9, a0, v8
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv1i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsext.vf2 v10, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v10, a0, v9
+; RV64-NEXT: vmv.v.v v8, v10
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -133,12 +171,21 @@ define <vscale x 2 x i64> @vwmacc_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
}
define <vscale x 2 x i64> @vwmacc_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwmacc.vx v10, a0, v8
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmacc_vx_nxv2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwmacc.vx v10, a0, v8
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmacc_vx_nxv2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v12, a0, v10
+; RV64-NEXT: vmv.v.v v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -165,12 +212,22 @@ define <vscale x 2 x i64> @vwmaccu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x
}
define <vscale x 2 x i64> @vwmaccu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwmaccu.vx v10, a0, v8
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccu_vx_nxv2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwmaccu.vx v10, a0, v8
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vzext.vf2 v12, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v12, a0, v10
+; RV64-NEXT: vmv.v.v v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -197,12 +254,21 @@ define <vscale x 2 x i64> @vwmaccsu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x
}
define <vscale x 2 x i64> @vwmaccsu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwmaccsu.vx v10, a0, v8
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccsu_vx_nxv2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwmaccsu.vx v10, a0, v8
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vzext.vf2 v12, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v12, a0, v10
+; RV64-NEXT: vmv.v.v v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -214,12 +280,22 @@ define <vscale x 2 x i64> @vwmaccsu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <
}
define <vscale x 2 x i64> @vwmaccus_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwmaccus.vx v10, a0, v8
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccus_vx_nxv2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwmaccus.vx v10, a0, v8
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v12, a0, v10
+; RV64-NEXT: vmv.v.v v8, v12
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -246,12 +322,21 @@ define <vscale x 4 x i64> @vwmacc_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
}
define <vscale x 4 x i64> @vwmacc_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwmacc.vx v12, a0, v8
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmacc_vx_nxv4i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwmacc.vx v12, a0, v8
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmacc_vx_nxv4i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v16, a0, v12
+; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -278,12 +363,22 @@ define <vscale x 4 x i64> @vwmaccu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x
}
define <vscale x 4 x i64> @vwmaccu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwmaccu.vx v12, a0, v8
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccu_vx_nxv4i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwmaccu.vx v12, a0, v8
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv4i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vzext.vf2 v16, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v16, a0, v12
+; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -310,12 +405,21 @@ define <vscale x 4 x i64> @vwmaccsu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x
}
define <vscale x 4 x i64> @vwmaccsu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwmaccsu.vx v12, a0, v8
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccsu_vx_nxv4i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwmaccsu.vx v12, a0, v8
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv4i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vzext.vf2 v16, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v16, a0, v12
+; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -327,12 +431,22 @@ define <vscale x 4 x i64> @vwmaccsu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <
}
define <vscale x 4 x i64> @vwmaccus_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwmaccus.vx v12, a0, v8
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccus_vx_nxv4i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwmaccus.vx v12, a0, v8
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv4i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v16, a0, v12
+; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -359,12 +473,21 @@ define <vscale x 8 x i64> @vwmacc_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
}
define <vscale x 8 x i64> @vwmacc_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwmacc.vx v16, a0, v8
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmacc_vx_nxv8i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwmacc.vx v16, a0, v8
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmacc_vx_nxv8i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsext.vf2 v24, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v24, a0, v16
+; RV64-NEXT: vmv.v.v v8, v24
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -391,12 +514,22 @@ define <vscale x 8 x i64> @vwmaccu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x
}
define <vscale x 8 x i64> @vwmaccu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwmaccu.vx v16, a0, v8
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccu_vx_nxv8i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwmaccu.vx v16, a0, v8
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv8i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vzext.vf2 v24, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v24, a0, v16
+; RV64-NEXT: vmv.v.v v8, v24
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -423,12 +556,21 @@ define <vscale x 8 x i64> @vwmaccsu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x
}
define <vscale x 8 x i64> @vwmaccsu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwmaccsu.vx v16, a0, v8
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccsu_vx_nxv8i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwmaccsu.vx v16, a0, v8
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv8i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vzext.vf2 v24, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmadd.vx v24, a0, v16
+; RV64-NEXT: vmv.v.v v8, v24
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -440,12 +582,22 @@ define <vscale x 8 x i64> @vwmaccsu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <
}
define <vscale x 8 x i64> @vwmaccus_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwmaccus.vx v16, a0, v8
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmaccus_vx_nxv8i32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwmaccus.vx v16, a0, v8
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv8i32:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsext.vf2 v24, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmadd.vx v24, a0, v16
+; RV64-NEXT: vmv.v.v v8, v24
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
index 513cbe3d0e4d..6c53f037ff95 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i64> @vwmul_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwmul_vv_nxv1i64:
@@ -42,12 +42,20 @@ define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x
}
define <vscale x 1 x i64> @vwmul_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwmul.vx v9, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmul_vx_nxv1i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwmul.vx v9, v8, a0
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmul_vx_nxv1i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsext.vf2 v9, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmul.vx v8, v9, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -57,12 +65,21 @@ define <vscale x 1 x i64> @vwmul_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
}
define <vscale x 1 x i64> @vwmulu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vx v9, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulu_vx_nxv1i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwmulu.vx v9, v8, a0
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulu_vx_nxv1i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vzext.vf2 v9, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v9, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -72,12 +89,21 @@ define <vscale x 1 x i64> @vwmulu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
}
define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v9, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulsu_vx_nxv1i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT: vwmulsu.vx v9, v8, a0
+; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv1i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT: vsext.vf2 v9, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v9, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -126,12 +152,20 @@ define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x
}
define <vscale x 2 x i64> @vwmul_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwmul.vx v10, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmul_vx_nxv2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwmul.vx v10, v8, a0
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmul_vx_nxv2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsext.vf2 v10, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmul.vx v8, v10, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -141,12 +175,21 @@ define <vscale x 2 x i64> @vwmul_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
}
define <vscale x 2 x i64> @vwmulu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwmulu.vx v10, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulu_vx_nxv2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwmulu.vx v10, v8, a0
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulu_vx_nxv2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vzext.vf2 v10, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v10, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -156,12 +199,21 @@ define <vscale x 2 x i64> @vwmulu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
}
define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vx v10, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulsu_vx_nxv2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT: vwmulsu.vx v10, v8, a0
+; RV32-NEXT: vmv2r.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT: vsext.vf2 v10, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v10, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -210,12 +262,20 @@ define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x
}
define <vscale x 4 x i64> @vwmul_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwmul.vx v12, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmul_vx_nxv4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwmul.vx v12, v8, a0
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmul_vx_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmul.vx v8, v12, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -225,12 +285,21 @@ define <vscale x 4 x i64> @vwmul_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
}
define <vscale x 4 x i64> @vwmulu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwmulu.vx v12, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulu_vx_nxv4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwmulu.vx v12, v8, a0
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulu_vx_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vzext.vf2 v12, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v12, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -240,12 +309,21 @@ define <vscale x 4 x i64> @vwmulu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
}
define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v12, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulsu_vx_nxv4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT: vwmulsu.vx v12, v8, a0
+; RV32-NEXT: vmv4r.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v12, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -294,12 +372,20 @@ define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x
}
define <vscale x 8 x i64> @vwmul_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwmul.vx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmul_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwmul.vx v16, v8, a0
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmul_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: vmul.vx v8, v16, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -309,12 +395,21 @@ define <vscale x 8 x i64> @vwmul_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
}
define <vscale x 8 x i64> @vwmulu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwmulu.vx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulu_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwmulu.vx v16, v8, a0
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulu_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vzext.vf2 v16, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v16, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -324,12 +419,21 @@ define <vscale x 8 x i64> @vwmulu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
}
define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwmulsu.vx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vwmulsu_vx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT: vwmulsu.vx v16, v8, a0
+; RV32-NEXT: vmv8r.v v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmul.vx v8, v16, a0
+; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
index d25a574a438a..419c70db9707 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK64
define <vscale x 1 x i64> @vwsub_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwsub_vv_nxv1i64:
@@ -29,12 +29,20 @@ define <vscale x 1 x i64> @vwsubu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1
}
define <vscale x 1 x i64> @vwsub_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.vx v9, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_vx_nxv1i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT: vwsub.vx v9, v8, a0
+; CHECK32-NEXT: vmv1r.v v8, v9
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv1i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT: vsext.vf2 v9, v8
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsub.vx v8, v9, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -44,12 +52,21 @@ define <vscale x 1 x i64> @vwsub_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
}
define <vscale x 1 x i64> @vwsubu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vx v9, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_vx_nxv1i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT: vwsubu.vx v9, v8, a0
+; CHECK32-NEXT: vmv1r.v v8, v9
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv1i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT: vzext.vf2 v9, v8
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsub.vx v8, v9, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
@@ -83,11 +100,18 @@ define <vscale x 1 x i64> @vwsubu_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
}
define <vscale x 1 x i64> @vwsub_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_wx_nxv1i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT: vwsub.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv1i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -96,11 +120,19 @@ define <vscale x 1 x i64> @vwsub_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
}
define <vscale x 1 x i64> @vwsubu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_wx_nxv1i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT: vwsubu.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv1i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
@@ -135,12 +167,20 @@ define <vscale x 2 x i64> @vwsubu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2
}
define <vscale x 2 x i64> @vwsub_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.vx v10, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_vx_nxv2i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT: vwsub.vx v10, v8, a0
+; CHECK32-NEXT: vmv2r.v v8, v10
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv2i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT: vsext.vf2 v10, v8
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsub.vx v8, v10, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -150,12 +190,21 @@ define <vscale x 2 x i64> @vwsub_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
}
define <vscale x 2 x i64> @vwsubu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.vx v10, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v10
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_vx_nxv2i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT: vwsubu.vx v10, v8, a0
+; CHECK32-NEXT: vmv2r.v v8, v10
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv2i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT: vzext.vf2 v10, v8
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsub.vx v8, v10, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
@@ -189,11 +238,18 @@ define <vscale x 2 x i64> @vwsubu_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
}
define <vscale x 2 x i64> @vwsub_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_wx_nxv2i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT: vwsub.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv2i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -202,11 +258,19 @@ define <vscale x 2 x i64> @vwsub_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
}
define <vscale x 2 x i64> @vwsubu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_wx_nxv2i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT: vwsubu.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv2i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
@@ -241,12 +305,20 @@ define <vscale x 4 x i64> @vwsubu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4
}
define <vscale x 4 x i64> @vwsub_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.vx v12, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_vx_nxv4i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT: vwsub.vx v12, v8, a0
+; CHECK32-NEXT: vmv4r.v v8, v12
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv4i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT: vsext.vf2 v12, v8
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsub.vx v8, v12, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -256,12 +328,21 @@ define <vscale x 4 x i64> @vwsub_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
}
define <vscale x 4 x i64> @vwsubu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.vx v12, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_vx_nxv4i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT: vwsubu.vx v12, v8, a0
+; CHECK32-NEXT: vmv4r.v v8, v12
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv4i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT: vzext.vf2 v12, v8
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsub.vx v8, v12, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
@@ -295,11 +376,18 @@ define <vscale x 4 x i64> @vwsubu_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
}
define <vscale x 4 x i64> @vwsub_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_wx_nxv4i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT: vwsub.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv4i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -308,11 +396,19 @@ define <vscale x 4 x i64> @vwsub_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
}
define <vscale x 4 x i64> @vwsubu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_wx_nxv4i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT: vwsubu.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv4i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
@@ -347,12 +443,20 @@ define <vscale x 8 x i64> @vwsubu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8
}
define <vscale x 8 x i64> @vwsub_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwsub.vx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_vx_nxv8i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT: vwsub.vx v16, v8, a0
+; CHECK32-NEXT: vmv8r.v v8, v16
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv8i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT: vsext.vf2 v16, v8
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsub.vx v8, v16, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -362,12 +466,21 @@ define <vscale x 8 x i64> @vwsub_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
}
define <vscale x 8 x i64> @vwsubu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwsubu.vx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_vx_nxv8i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT: vwsubu.vx v16, v8, a0
+; CHECK32-NEXT: vmv8r.v v8, v16
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv8i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT: vzext.vf2 v16, v8
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsub.vx v8, v16, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
@@ -401,11 +514,18 @@ define <vscale x 8 x i64> @vwsubu_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
}
define <vscale x 8 x i64> @vwsub_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwsub.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsub_wx_nxv8i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT: vwsub.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv8i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a0, a0
+; CHECK64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
@@ -414,11 +534,19 @@ define <vscale x 8 x i64> @vwsub_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
}
define <vscale x 8 x i64> @vwsubu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vwsubu.wx v8, v8, a0
-; CHECK-NEXT: ret
+; CHECK32-LABEL: vwsubu_wx_nxv8i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT: vwsubu.wx v8, v8, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv8i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: slli a0, a0, 32
+; CHECK64-NEXT: srli a0, a0, 32
+; CHECK64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT: vsub.vx v8, v8, a0
+; CHECK64-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
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