[llvm-branch-commits] [llvm] 8a8377e - Implementation of STBCX
Albion Fung via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jul 14 07:41:11 PDT 2021
Author: Albion Fung
Date: 2021-07-14T09:39:47-05:00
New Revision: 8a8377e1d2324f2631badbd02dc4ff0fd824ebb1
URL: https://github.com/llvm/llvm-project/commit/8a8377e1d2324f2631badbd02dc4ff0fd824ebb1
DIFF: https://github.com/llvm/llvm-project/commit/8a8377e1d2324f2631badbd02dc4ff0fd824ebb1.diff
LOG: Implementation of STBCX
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index 09769b3f974eb..a214c4e1cc7b3 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -58,6 +58,7 @@ BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*c", "")
BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
BUILTIN(__builtin_ppc_tw, "viiIUi", "")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b79b30d7a4cdb..a428f0c3a9f70 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -118,6 +118,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+ Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
Builder.defineMacro("__tw", "__builtin_ppc_tw");
Builder.defineMacro("__trap", "__builtin_ppc_trap");
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..b886f270615ed 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15575,6 +15575,21 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
case PPC::BI__builtin_ppc_ldarx:
case PPC::BI__builtin_ppc_lwarx:
return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+ case PPC::BI__builtin_ppc_stbcx: {
+ llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_stbcx);
+ Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+ auto Signed = getIntegerWidthAndSignedness(CGM.getContext(),
+ E->getArg(1)->getType()).Signed;
+
+ if (Signed) {
+ dbgs() << "SIGNED\n";
+ Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+ } else {
+ dbgs() << "UNSIGNED\n";
+ Ops[1] = Builder.CreateZExt(Ops[1], Int32Ty);
+ }
+ return Builder.CreateCall(F, Ops);
+ }
}
}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
index 4ffa29a094558..7ae412a6c4803 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -18,3 +18,18 @@ int test_stwcx(volatile int* a, int val) {
// CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val)
return __stwcx(a, val);
}
+
+int test_stbcx_signed(volatile char* a, signed char val) {
+ // TODO: fix current zext code gen to sext
+ // CHECK-LABEL: @test_stbcx_signed
+ // CHECK: %0 = sext i8 %b to i32
+ // CHECK: tail call i32 @llvm.ppc.stbcx(i8 *a, i32 %0)
+ return __stbcx(a, val);
+}
+
+int test_stbcx_unsigned(volatile char* a, unsigned char val) {
+ // CHECK-LABEL: @test_stbcx_unsigned
+ // CHECK: %0 = zext i8 %b to i32
+ // CHECK: tail call i32 @llvm.ppc.stbcx(i8 *a, i32 %0)
+ return __stbcx(a, val);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b021b43afe595..d95823ef59c52 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1565,6 +1565,7 @@ let TargetPrefix = "ppc" in {
def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrWriteMem]>;
+ def int_ppc_stbcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>;
// compare
def int_ppc_cmpeqb
: GCCBuiltin<"__builtin_ppc_cmpeqb">,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index d97881fe818bc..2e8ca2df241e0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5445,3 +5445,5 @@ def : Pat<(int_ppc_fctudz f64:$A),
(XSCVDPUXDS $A)>;
def : Pat<(int_ppc_fctuwz f64:$A),
(XSCVDPUXWS $A)>;
+def : Pat<(int_ppc_stbcx xoaddr:$dst, gprc:$A),
+ (STBCX gprc:$A, xoaddr:$dst)>;
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
index 7b1651008f76b..783859f0a04e5 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -50,3 +50,37 @@ entry:
%1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %b)
ret i32 %1
}
+
+declare i32 @llvm.ppc.stbcx(i8*, i32)
+; signed test case
+define dso_local signext i32 @test_stbcx_signed(i8* %a, i8 signext %b) {
+; TODO: regenerate this test case
+; CHECK-32-LABEL: test_stbcx_signed:
+; CHECK-32: extsb
+; CHECK-32: stbcx.
+
+; CHECK-64-LABEL: test_stbcx_signed:
+; CHECK-64: extsb
+; CHECK-64: stbcx.
+entry:
+ ; TODO: this should be sext
+ %0 = zext i8 %b to i32
+ %1 = tail call i32 @llvm.ppc.stbcx(i8* %a, i32 %0)
+ ret i32 %1
+}
+
+; unsigned test case
+define dso_local signext i32 @test_stbcx_unsigned(i8* %a, i8 zeroext %b) {
+; TODO: regenerate this test case
+; CHECK-32-LABEL: test_stbcx_unsigned:
+; CHECK-32: clrlwi
+; CHECK-32: stbcx.
+
+; CHECK-64-LABEL: test_stbcx_unsigned:
+; CHECK-64: clrlwi
+; CHECK-64: stbcx.
+entry:
+ %0 = zext i8 %b to i32
+ %1 = tail call i32 @llvm.ppc.stbcx(i8* %a, i32 %0)
+ ret i32 %1
+}
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