[llvm-branch-commits] [llvm] e996f1d - [RISCV] Add another isel pattern for slliu.w.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-20T14:54:40-08:00
New Revision: e996f1d4194bccf1c8ca984d695b848c0093bc23

URL: https://github.com/llvm/llvm-project/commit/e996f1d4194bccf1c8ca984d695b848c0093bc23
DIFF: https://github.com/llvm/llvm-project/commit/e996f1d4194bccf1c8ca984d695b848c0093bc23.diff

LOG: [RISCV] Add another isel pattern for slliu.w.

Previously we only matched (and (shl X, C1), 0xffffffff << C1)
which matches the InstCombine canonicalization order. But its
possible to see (shl (and X, 0xffffffff), C1) if the pattern
is introduced in SelectionDAG. For example, through expansion of
a GEP.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    llvm/test/CodeGen/RISCV/rv64Zbb.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index c7bfe99bc712..205f8e65e655 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -842,6 +842,8 @@ def : Pat<(and (add GPR:$rs, simm12:$simm12), (i64 0xFFFFFFFF)),
           (ADDIWU GPR:$rs, simm12:$simm12)>;
 def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
+def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
+          (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(and (add GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)),
           (ADDWU GPR:$rs1, GPR:$rs2)>;
 def : Pat<(and (sub GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)),

diff  --git a/llvm/test/CodeGen/RISCV/rv64Zbb.ll b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
index f4ac43c17d92..56ae050342ee 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
@@ -1070,8 +1070,7 @@ define i128 @slliuw_2(i32 signext %0, i128* %1) {
 ;
 ; RV64IB-LABEL: slliuw_2:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    zext.w a0, a0
-; RV64IB-NEXT:    slli a0, a0, 4
+; RV64IB-NEXT:    slliu.w a0, a0, 4
 ; RV64IB-NEXT:    add a1, a1, a0
 ; RV64IB-NEXT:    ld a0, 0(a1)
 ; RV64IB-NEXT:    ld a1, 8(a1)
@@ -1079,8 +1078,7 @@ define i128 @slliuw_2(i32 signext %0, i128* %1) {
 ;
 ; RV64IBB-LABEL: slliuw_2:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    zext.w a0, a0
-; RV64IBB-NEXT:    slli a0, a0, 4
+; RV64IBB-NEXT:    slliu.w a0, a0, 4
 ; RV64IBB-NEXT:    add a1, a1, a0
 ; RV64IBB-NEXT:    ld a0, 0(a1)
 ; RV64IBB-NEXT:    ld a1, 8(a1)