[llvm-branch-commits] [llvm] 0f8386c - [RISCV] Add addu.w and slliu.w test that uses getelementptr with zero extended indices.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-20T14:54:40-08:00
New Revision: 0f8386c4f6aa804fe43814fcb3ae29d271da82d7

URL: https://github.com/llvm/llvm-project/commit/0f8386c4f6aa804fe43814fcb3ae29d271da82d7
DIFF: https://github.com/llvm/llvm-project/commit/0f8386c4f6aa804fe43814fcb3ae29d271da82d7.diff

LOG: [RISCV] Add addu.w and slliu.w test that uses getelementptr with zero extended indices.

This is closer to the kind of code that these intrinsics are
targeted at. Note we fail to match slliu.w here because our pattern
looks for (and (shl X, C1), 0xffffffff << C1) rather than
(shl (and X, 0xffffffff), C1). I'll fix this in a follow up
commit.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64Zbb.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64Zbb.ll b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
index 92ed8e7ed5fa..f4ac43c17d92 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
@@ -1057,6 +1057,40 @@ define i64 @slliuw(i64 %a) nounwind {
   ret i64 %shl
 }
 
+define i128 @slliuw_2(i32 signext %0, i128* %1) {
+; RV64I-LABEL: slliuw_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    slli a0, a0, 4
+; RV64I-NEXT:    add a1, a1, a0
+; RV64I-NEXT:    ld a0, 0(a1)
+; RV64I-NEXT:    ld a1, 8(a1)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: slliuw_2:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    zext.w a0, a0
+; RV64IB-NEXT:    slli a0, a0, 4
+; RV64IB-NEXT:    add a1, a1, a0
+; RV64IB-NEXT:    ld a0, 0(a1)
+; RV64IB-NEXT:    ld a1, 8(a1)
+; RV64IB-NEXT:    ret
+;
+; RV64IBB-LABEL: slliuw_2:
+; RV64IBB:       # %bb.0:
+; RV64IBB-NEXT:    zext.w a0, a0
+; RV64IBB-NEXT:    slli a0, a0, 4
+; RV64IBB-NEXT:    add a1, a1, a0
+; RV64IBB-NEXT:    ld a0, 0(a1)
+; RV64IBB-NEXT:    ld a1, 8(a1)
+; RV64IBB-NEXT:    ret
+  %3 = zext i32 %0 to i64
+  %4 = getelementptr inbounds i128, i128* %1, i64 %3
+  %5 = load i128, i128* %4
+  ret i128 %5
+}
+
 ; We select a i32 add that zero-extends the result on RV64 as addwu
 
 define zeroext i32 @zext_add_to_addwu(i32 signext %a, i32 signext %b) nounwind {
@@ -1169,6 +1203,32 @@ define i64 @adduw(i64 %a, i64 %b) nounwind {
   ret i64 %add
 }
 
+define signext i8 @adduw_2(i32 signext %0, i8* %1) {
+; RV64I-LABEL: adduw_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    lb a0, 0(a0)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: adduw_2:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addu.w a0, a1, a0
+; RV64IB-NEXT:    lb a0, 0(a0)
+; RV64IB-NEXT:    ret
+;
+; RV64IBB-LABEL: adduw_2:
+; RV64IBB:       # %bb.0:
+; RV64IBB-NEXT:    addu.w a0, a1, a0
+; RV64IBB-NEXT:    lb a0, 0(a0)
+; RV64IBB-NEXT:    ret
+  %3 = zext i32 %0 to i64
+  %4 = getelementptr inbounds i8, i8* %1, i64 %3
+  %5 = load i8, i8* %4
+  ret i8 %5
+}
+
 define i64 @subuw(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: subuw:
 ; RV64I:       # %bb.0: