[llvm-branch-commits] [clang] ad55d5c - Simplify vectorcall argument classification of HVAs, NFC
Reid Kleckner via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jan 7 11:19:11 PST 2021
Author: Reid Kleckner
Date: 2021-01-07T11:14:18-08:00
New Revision: ad55d5c3f32f6598f8ac30b68f4961d82cdb1fed
URL: https://github.com/llvm/llvm-project/commit/ad55d5c3f32f6598f8ac30b68f4961d82cdb1fed
DIFF: https://github.com/llvm/llvm-project/commit/ad55d5c3f32f6598f8ac30b68f4961d82cdb1fed.diff
LOG: Simplify vectorcall argument classification of HVAs, NFC
This reduces the number of `WinX86_64ABIInfo::classify` call sites from
3 to 1. The call sites were similar, but passed different values for
FreeSSERegs. Use variables instead of `if`s to manage that argument.
Added:
Modified:
clang/lib/CodeGen/TargetInfo.cpp
Removed:
################################################################################
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index c6d8942208e8..d36c7344e284 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -1089,11 +1089,6 @@ struct CCState {
unsigned FreeSSERegs = 0;
};
-enum {
- // Vectorcall only allows the first 6 parameters to be passed in registers.
- VectorcallMaxParamNumAsReg = 6
-};
-
/// X86_32ABIInfo - The X86-32 ABI information.
class X86_32ABIInfo : public SwiftABIInfo {
enum Class {
@@ -2405,10 +2400,8 @@ class WinX86_64ABIInfo : public SwiftABIInfo {
private:
ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
bool IsVectorCall, bool IsRegCall) const;
- ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
- const ABIArgInfo ¤t) const;
- void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
- bool IsVectorCall, bool IsRegCall) const;
+ ABIArgInfo reclassifyHvaArgForVectorCall(QualType Ty, unsigned &FreeSSERegs,
+ const ABIArgInfo ¤t) const;
X86AVXABILevel AVXLevel;
@@ -4163,10 +4156,8 @@ Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
/*allowHigherAlign*/ false);
}
-ABIArgInfo
-WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
- const ABIArgInfo ¤t) const {
- // Assumes vectorCall calling convention.
+ABIArgInfo WinX86_64ABIInfo::reclassifyHvaArgForVectorCall(
+ QualType Ty, unsigned &FreeSSERegs, const ABIArgInfo ¤t) const {
const Type *Base = nullptr;
uint64_t NumElts = 0;
@@ -4299,31 +4290,6 @@ ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
return ABIArgInfo::getDirect();
}
-void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
- unsigned FreeSSERegs,
- bool IsVectorCall,
- bool IsRegCall) const {
- unsigned Count = 0;
- for (auto &I : FI.arguments()) {
- // Vectorcall in x64 only permits the first 6 arguments to be passed
- // as XMM/YMM registers.
- if (Count < VectorcallMaxParamNumAsReg)
- I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
- else {
- // Since these cannot be passed in registers, pretend no registers
- // are left.
- unsigned ZeroSSERegsAvail = 0;
- I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
- IsVectorCall, IsRegCall);
- }
- ++Count;
- }
-
- for (auto &I : FI.arguments()) {
- I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
- }
-}
-
void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
const unsigned CC = FI.getCallingConvention();
bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
@@ -4358,13 +4324,25 @@ void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
FreeSSERegs = 16;
}
+ unsigned ArgNum = 0;
+ unsigned ZeroSSERegs = 0;
+ for (auto &I : FI.arguments()) {
+ // Vectorcall in x64 only permits the first 6 arguments to be passed as
+ // XMM/YMM registers. After the sixth argument, pretend no vector
+ // registers are left.
+ unsigned *MaybeFreeSSERegs =
+ (IsVectorCall && ArgNum >= 6) ? &ZeroSSERegs : &FreeSSERegs;
+ I.info =
+ classify(I.type, *MaybeFreeSSERegs, false, IsVectorCall, IsRegCall);
+ ++ArgNum;
+ }
+
if (IsVectorCall) {
- computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
- } else {
+ // For vectorcall, assign aggregate HVAs to any free vector registers in a
+ // second pass.
for (auto &I : FI.arguments())
- I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
+ I.info = reclassifyHvaArgForVectorCall(I.type, FreeSSERegs, I.info);
}
-
}
Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
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