[llvm-branch-commits] [llvm] 4c7148d - [SLP] remove opcode identifier for reduction; NFC

Sanjay Patel via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Thu Jan 7 11:11:34 PST 2021


Author: Sanjay Patel
Date: 2021-01-07T14:07:27-05:00
New Revision: 4c7148d75cd7e75f169251cdab3e013819344cfd

URL: https://github.com/llvm/llvm-project/commit/4c7148d75cd7e75f169251cdab3e013819344cfd
DIFF: https://github.com/llvm/llvm-project/commit/4c7148d75cd7e75f169251cdab3e013819344cfd.diff

LOG: [SLP] remove opcode identifier for reduction; NFC

Another step towards allowing intrinsics in reduction matching.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 8d6453f277ea..c8e5fdb458ff 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -772,7 +772,7 @@ class BoUpSLP {
   /// effectively impossible for the backend to undo.
   /// TODO: If load combining is allowed in the IR optimizer, this analysis
   ///       may not be necessary.
-  bool isLoadCombineReductionCandidate(unsigned ReductionOpcode) const;
+  bool isLoadCombineReductionCandidate(RecurKind RdxKind) const;
 
   /// Assume that a vector of stores of bitwise-or/shifted/zexted loaded values
   /// can be load combined in the backend. Load combining may not be allowed in
@@ -3896,8 +3896,8 @@ static bool isLoadCombineCandidateImpl(Value *Root, unsigned NumElts,
   return true;
 }
 
-bool BoUpSLP::isLoadCombineReductionCandidate(unsigned RdxOpcode) const {
-  if (RdxOpcode != Instruction::Or)
+bool BoUpSLP::isLoadCombineReductionCandidate(RecurKind RdxKind) const {
+  if (RdxKind != RecurKind::Or)
     return false;
 
   unsigned NumElts = VectorizableTree[0]->Scalars.size();
@@ -6987,7 +6987,7 @@ class HorizontalReduction {
       }
       if (V.isTreeTinyAndNotFullyVectorizable())
         break;
-      if (V.isLoadCombineReductionCandidate(RdxTreeInst.getOpcode()))
+      if (V.isLoadCombineReductionCandidate(RdxTreeInst.getKind()))
         break;
 
       V.computeMinimumValueSizes();


        


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