[llvm-branch-commits] [llvm] a015635 - [Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns
Simon Pilgrim via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Nov 25 11:06:37 PST 2020
Author: Simon Pilgrim
Date: 2020-11-25T19:02:17Z
New Revision: a0156356296b54dc071405332a517695b1881bc1
URL: https://github.com/llvm/llvm-project/commit/a0156356296b54dc071405332a517695b1881bc1
DIFF: https://github.com/llvm/llvm-project/commit/a0156356296b54dc071405332a517695b1881bc1.diff
LOG: [Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns
This should handle the basic integer min/max handling - the HVX ops are still TODO.
This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.
Differential Revision: https://reviews.llvm.org/D92112
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonPatterns.td
llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index b2fc79215c1e..b60758a8be8a 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1517,8 +1517,11 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setMinimumJumpTableEntries(std::numeric_limits<unsigned>::max());
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
- setOperationAction(ISD::ABS, MVT::i32, Legal);
- setOperationAction(ISD::ABS, MVT::i64, Legal);
+ for (unsigned LegalIntOp :
+ {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) {
+ setOperationAction(LegalIntOp, MVT::i32, Legal);
+ setOperationAction(LegalIntOp, MVT::i64, Legal);
+ }
// Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
// but they only operate on i64.
@@ -1683,6 +1686,13 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal);
}
+ for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
+ setOperationAction(ISD::SMIN, VT, Legal);
+ setOperationAction(ISD::SMAX, VT, Legal);
+ setOperationAction(ISD::UMIN, VT, Legal);
+ setOperationAction(ISD::UMAX, VT, Legal);
+ }
+
// Custom lower unaligned loads.
// Also, for both loads and stores, verify the alignment of the address
// in case it is a compile-time constant. This is a usability feature to
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 348cef29c305..fa91f7a31b14 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -366,12 +366,14 @@ multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> {
def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>;
}
-
// Frags for commonly used SDNodes.
def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>;
+def Smin: pf2<smin>; def Smax: pf2<smax>;
+def Umin: pf2<umin>; def Umax: pf2<umax>;
+
def Rol: pf2<rotl>;
// --(1) Immediate -------------------------------------------------------
@@ -924,25 +926,14 @@ let AddedComplexity = 200 in {
defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>;
}
-let AddedComplexity = 200 in {
- defm: MinMax_pats<A2_min, A2_max, select, setgt, i1, I32>;
- defm: MinMax_pats<A2_min, A2_max, select, setge, i1, I32>;
- defm: MinMax_pats<A2_max, A2_min, select, setlt, i1, I32>;
- defm: MinMax_pats<A2_max, A2_min, select, setle, i1, I32>;
- defm: MinMax_pats<A2_minu, A2_maxu, select, setugt, i1, I32>;
- defm: MinMax_pats<A2_minu, A2_maxu, select, setuge, i1, I32>;
- defm: MinMax_pats<A2_maxu, A2_minu, select, setult, i1, I32>;
- defm: MinMax_pats<A2_maxu, A2_minu, select, setule, i1, I32>;
-
- defm: MinMax_pats<A2_minp, A2_maxp, select, setgt, i1, I64>;
- defm: MinMax_pats<A2_minp, A2_maxp, select, setge, i1, I64>;
- defm: MinMax_pats<A2_maxp, A2_minp, select, setlt, i1, I64>;
- defm: MinMax_pats<A2_maxp, A2_minp, select, setle, i1, I64>;
- defm: MinMax_pats<A2_minup, A2_maxup, select, setugt, i1, I64>;
- defm: MinMax_pats<A2_minup, A2_maxup, select, setuge, i1, I64>;
- defm: MinMax_pats<A2_maxup, A2_minup, select, setult, i1, I64>;
- defm: MinMax_pats<A2_maxup, A2_minup, select, setule, i1, I64>;
-}
+def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>;
+def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>;
+def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>;
+def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>;
+def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>;
+def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>;
+def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>;
+def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>;
let AddedComplexity = 100 in {
defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>;
@@ -958,18 +949,20 @@ let AddedComplexity = 100, Predicates = [HasV67] in {
defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>;
}
-defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setgt, v8i1, V8I8>;
-defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setge, v8i1, V8I8>;
-defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setgt, v4i1, V4I16>;
-defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setge, v4i1, V4I16>;
-defm: MinMax_pats<A2_vminw, A2_vmaxw, vselect, setgt, v2i1, V2I32>;
-defm: MinMax_pats<A2_vminw, A2_vmaxw, vselect, setge, v2i1, V2I32>;
-defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setugt, v8i1, V8I8>;
-defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setuge, v8i1, V8I8>;
-defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setugt, v4i1, V4I16>;
-defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setuge, v4i1, V4I16>;
-defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setugt, v2i1, V2I32>;
-defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setuge, v2i1, V2I32>;
+def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>;
+def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>;
+def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>;
+def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>;
+
+def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>;
+def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>;
+def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>;
+def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>;
+
+def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>;
+def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>;
+def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>;
+def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>;
// --(7) Insert/extract --------------------------------------------------
//
diff --git a/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll b/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll
index 53dec510a865..d175d8dd295c 100644
--- a/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll
+++ b/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll
@@ -3,7 +3,7 @@
; min
; CHECK-LABEL: test_00:
-; CHECK: r1:0 = vminb(r3:2,r1:0)
+; CHECK: r1:0 = vminb(r1:0,r3:2)
define <8 x i8> @test_00(<8 x i8> %a0, <8 x i8> %a1) #0 {
%v0 = icmp slt <8 x i8> %a0, %a1
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -19,7 +19,7 @@ define <8 x i8> @test_01(<8 x i8> %a0, <8 x i8> %a1) #0 {
}
; CHECK-LABEL: test_02:
-; CHECK: r1:0 = vminh(r3:2,r1:0)
+; CHECK: r1:0 = vminh(r1:0,r3:2)
define <4 x i16> @test_02(<4 x i16> %a0, <4 x i16> %a1) #0 {
%v0 = icmp slt <4 x i16> %a0, %a1
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -35,7 +35,7 @@ define <4 x i16> @test_03(<4 x i16> %a0, <4 x i16> %a1) #0 {
}
; CHECK-LABEL: test_04:
-; CHECK: r1:0 = vminw(r3:2,r1:0)
+; CHECK: r1:0 = vminw(r1:0,r3:2)
define <2 x i32> @test_04(<2 x i32> %a0, <2 x i32> %a1) #0 {
%v0 = icmp slt <2 x i32> %a0, %a1
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
@@ -53,7 +53,7 @@ define <2 x i32> @test_05(<2 x i32> %a0, <2 x i32> %a1) #0 {
; minu
; CHECK-LABEL: test_06:
-; CHECK: r1:0 = vminub(r3:2,r1:0)
+; CHECK: r1:0 = vminub(r1:0,r3:2)
define <8 x i8> @test_06(<8 x i8> %a0, <8 x i8> %a1) #0 {
%v0 = icmp ult <8 x i8> %a0, %a1
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -69,7 +69,7 @@ define <8 x i8> @test_07(<8 x i8> %a0, <8 x i8> %a1) #0 {
}
; CHECK-LABEL: test_08:
-; CHECK: r1:0 = vminuh(r3:2,r1:0)
+; CHECK: r1:0 = vminuh(r1:0,r3:2)
define <4 x i16> @test_08(<4 x i16> %a0, <4 x i16> %a1) #0 {
%v0 = icmp ult <4 x i16> %a0, %a1
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -85,7 +85,7 @@ define <4 x i16> @test_09(<4 x i16> %a0, <4 x i16> %a1) #0 {
}
; CHECK-LABEL: test_0a:
-; CHECK: r1:0 = vminuw(r3:2,r1:0)
+; CHECK: r1:0 = vminuw(r1:0,r3:2)
define <2 x i32> @test_0a(<2 x i32> %a0, <2 x i32> %a1) #0 {
%v0 = icmp ult <2 x i32> %a0, %a1
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
@@ -111,7 +111,7 @@ define <8 x i8> @test_0c(<8 x i8> %a0, <8 x i8> %a1) #0 {
}
; CHECK-LABEL: test_0d:
-; CHECK: r1:0 = vmaxb(r3:2,r1:0)
+; CHECK: r1:0 = vmaxb(r1:0,r3:2)
define <8 x i8> @test_0d(<8 x i8> %a0, <8 x i8> %a1) #0 {
%v0 = icmp sge <8 x i8> %a0, %a1
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -127,7 +127,7 @@ define <4 x i16> @test_0e(<4 x i16> %a0, <4 x i16> %a1) #0 {
}
; CHECK-LABEL: test_0f:
-; CHECK: r1:0 = vmaxh(r3:2,r1:0)
+; CHECK: r1:0 = vmaxh(r1:0,r3:2)
define <4 x i16> @test_0f(<4 x i16> %a0, <4 x i16> %a1) #0 {
%v0 = icmp sge <4 x i16> %a0, %a1
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -143,7 +143,7 @@ define <2 x i32> @test_10(<2 x i32> %a0, <2 x i32> %a1) #0 {
}
; CHECK-LABEL: test_11:
-; CHECK: r1:0 = vmaxw(r3:2,r1:0)
+; CHECK: r1:0 = vmaxw(r1:0,r3:2)
define <2 x i32> @test_11(<2 x i32> %a0, <2 x i32> %a1) #0 {
%v0 = icmp sge <2 x i32> %a0, %a1
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
@@ -161,7 +161,7 @@ define <8 x i8> @test_12(<8 x i8> %a0, <8 x i8> %a1) #0 {
}
; CHECK-LABEL: test_13:
-; CHECK: r1:0 = vmaxub(r3:2,r1:0)
+; CHECK: r1:0 = vmaxub(r1:0,r3:2)
define <8 x i8> @test_13(<8 x i8> %a0, <8 x i8> %a1) #0 {
%v0 = icmp uge <8 x i8> %a0, %a1
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -177,7 +177,7 @@ define <4 x i16> @test_14(<4 x i16> %a0, <4 x i16> %a1) #0 {
}
; CHECK-LABEL: test_15:
-; CHECK: r1:0 = vmaxuh(r3:2,r1:0)
+; CHECK: r1:0 = vmaxuh(r1:0,r3:2)
define <4 x i16> @test_15(<4 x i16> %a0, <4 x i16> %a1) #0 {
%v0 = icmp uge <4 x i16> %a0, %a1
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -193,7 +193,7 @@ define <2 x i32> @test_16(<2 x i32> %a0, <2 x i32> %a1) #0 {
}
; CHECK-LABEL: test_17:
-; CHECK: r1:0 = vmaxuw(r3:2,r1:0)
+; CHECK: r1:0 = vmaxuw(r1:0,r3:2)
define <2 x i32> @test_17(<2 x i32> %a0, <2 x i32> %a1) #0 {
%v0 = icmp uge <2 x i32> %a0, %a1
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
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