[llvm-branch-commits] [llvm] 5654a3d - [RISCV] Add test cases showing that we don't recognize the select form of NABS in SelectionDAGBuilder so we end up with branches. NFC

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-11-25T10:45:39-08:00
New Revision: 5654a3dd0add58984e2c3247c70946d2ae0175f6

URL: https://github.com/llvm/llvm-project/commit/5654a3dd0add58984e2c3247c70946d2ae0175f6
DIFF: https://github.com/llvm/llvm-project/commit/5654a3dd0add58984e2c3247c70946d2ae0175f6.diff

LOG: [RISCV] Add test cases showing that we don't recognize the select form of NABS in SelectionDAGBuilder so we end up with branches. NFC

There's a FIXME that it should produce (sub 0, (abs)).

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/neg-abs.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/neg-abs.ll b/llvm/test/CodeGen/RISCV/neg-abs.ll
index 2171a1d24a281..10290a0f8b894 100644
--- a/llvm/test/CodeGen/RISCV/neg-abs.ll
+++ b/llvm/test/CodeGen/RISCV/neg-abs.ll
@@ -24,6 +24,29 @@ define i32 @neg_abs32(i32 %x) {
   ret i32 %neg
 }
 
+define i32 @select_neg_abs32(i32 %x) {
+; RV32-LABEL: select_neg_abs32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    bltz a0, .LBB1_2
+; RV32-NEXT:  # %bb.1:
+; RV32-NEXT:    neg a0, a0
+; RV32-NEXT:  .LBB1_2:
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: select_neg_abs32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a1, a0
+; RV64-NEXT:    bltz a1, .LBB1_2
+; RV64-NEXT:  # %bb.1:
+; RV64-NEXT:    negw a0, a0
+; RV64-NEXT:  .LBB1_2:
+; RV64-NEXT:    ret
+  %1 = icmp slt i32 %x, 0
+  %2 = sub nsw i32 0, %x
+  %3 = select i1 %1, i32 %x, i32 %2
+  ret i32 %3
+}
+
 define i64 @neg_abs64(i64 %x) {
 ; RV32-LABEL: neg_abs64:
 ; RV32:       # %bb.0:
@@ -46,3 +69,29 @@ define i64 @neg_abs64(i64 %x) {
   %neg = sub nsw i64 0, %abs
   ret i64 %neg
 }
+
+define i64 @select_neg_abs64(i64 %x) {
+; RV32-LABEL: select_neg_abs64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    bltz a1, .LBB3_2
+; RV32-NEXT:  # %bb.1:
+; RV32-NEXT:    snez a2, a0
+; RV32-NEXT:    add a1, a1, a2
+; RV32-NEXT:    neg a1, a1
+; RV32-NEXT:    neg a0, a0
+; RV32-NEXT:  .LBB3_2:
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: select_neg_abs64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    bltz a0, .LBB3_2
+; RV64-NEXT:  # %bb.1:
+; RV64-NEXT:    neg a0, a0
+; RV64-NEXT:  .LBB3_2:
+; RV64-NEXT:    ret
+  %1 = icmp slt i64 %x, 0
+  %2 = sub nsw i64 0, %x
+  %3 = select i1 %1, i64 %x, i64 %2
+  ret i64 %3
+}
+