[llvm-branch-commits] [llvm] 7a3e11f - [ARM] Add some NEON anyextend testing. NFC
David Green via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Dec 27 05:22:41 PST 2020
Author: David Green
Date: 2020-12-27T13:18:10Z
New Revision: 7a3e11fe96dd4ede17a194c6f407b7867a1137b8
URL: https://github.com/llvm/llvm-project/commit/7a3e11fe96dd4ede17a194c6f407b7867a1137b8
DIFF: https://github.com/llvm/llvm-project/commit/7a3e11fe96dd4ede17a194c6f407b7867a1137b8.diff
LOG: [ARM] Add some NEON anyextend testing. NFC
This cleans up and regenerates the NEON addw/addl/subw/subl/mlal etc
tests, adding some tests that turn the zext into anyextend using an and
mask.
Added:
Modified:
llvm/test/CodeGen/ARM/vadd.ll
llvm/test/CodeGen/ARM/vmla.ll
llvm/test/CodeGen/ARM/vmls.ll
llvm/test/CodeGen/ARM/vmul.ll
llvm/test/CodeGen/ARM/vsub.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/vadd.ll b/llvm/test/CodeGen/ARM/vadd.ll
index dd35dd1ccfb9..5f0ddd17c8c7 100644
--- a/llvm/test/CodeGen/ARM/vadd.ll
+++ b/llvm/test/CodeGen/ARM/vadd.ll
@@ -1,275 +1,370 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddi8:
-;CHECK: vadd.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = add <8 x i8> %tmp1, %tmp2
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddi16:
-;CHECK: vadd.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = add <4 x i16> %tmp1, %tmp2
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddi32:
-;CHECK: vadd.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = add <2 x i32> %tmp1, %tmp2
- ret <2 x i32> %tmp3
-}
-
-define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK-LABEL: vaddi64:
-;CHECK: vadd.i64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
- %tmp3 = add <1 x i64> %tmp1, %tmp2
- ret <1 x i64> %tmp3
-}
-
-define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vaddf32:
-;CHECK: vadd.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
- %tmp3 = fadd <2 x float> %tmp1, %tmp2
- ret <2 x float> %tmp3
-}
-
-define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddQi8:
-;CHECK: vadd.i8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = add <16 x i8> %tmp1, %tmp2
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddQi16:
-;CHECK: vadd.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = add <8 x i16> %tmp1, %tmp2
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddQi32:
-;CHECK: vadd.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = add <4 x i32> %tmp1, %tmp2
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vaddQi64:
-;CHECK: vadd.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
- %tmp3 = add <2 x i64> %tmp1, %tmp2
- ret <2 x i64> %tmp3
-}
-
-define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vaddQf32:
-;CHECK: vadd.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
- %tmp3 = fadd <4 x float> %tmp1, %tmp2
- ret <4 x float> %tmp3
-}
-
-define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vraddhni16:
-;CHECK: vraddhn.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vraddhni32:
-;CHECK: vraddhn.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vraddhni64:
-;CHECK: vraddhn.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
- %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @vaddhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind {
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vaddi8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i8 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <8 x i8> %A, %B
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vaddi16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i16 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <4 x i16> %A, %B
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vaddi32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i32 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <2 x i32> %A, %B
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vaddi64(<1 x i64> %A, <1 x i64> %B) {
+; CHECK-LABEL: vaddi64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i64 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <1 x i64> %A, %B
+ ret <1 x i64> %tmp3
+}
+
+define <2 x float> @vaddf32(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: vaddf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.f32 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = fadd <2 x float> %A, %B
+ ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vaddQi8(<16 x i8> %A, <16 x i8> %B) {
+; CHECK-LABEL: vaddQi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i8 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <16 x i8> %A, %B
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vaddQi16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vaddQi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i16 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <8 x i16> %A, %B
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vaddQi32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vaddQi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i32 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <4 x i32> %A, %B
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vaddQi64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vaddQi64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.i64 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = add <2 x i64> %A, %B
+ ret <2 x i64> %tmp3
+}
+
+define <4 x float> @vaddQf32(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: vaddQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vadd.f32 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = fadd <4 x float> %A, %B
+ ret <4 x float> %tmp3
+}
+
+define <8 x i8> @vraddhni16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vraddhni16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vraddhn.i16 d0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %A, <8 x i16> %B)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vraddhni32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vraddhni32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vraddhn.i32 d0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %A, <4 x i32> %B)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vraddhni64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vraddhni64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vraddhn.i64 d0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %A, <2 x i64> %B)
+ ret <2 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) readnone
+declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) readnone
+declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) readnone
+
+define <8 x i8> @vaddhni16_natural(<8 x i16> %A, <8 x i16> %B) {
; CHECK-LABEL: vaddhni16_natural:
-; CHECK: vaddhn.i16
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddhn.i16 d0, q0, q1
+; CHECK-NEXT: bx lr
%sum = add <8 x i16> %A, %B
%shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%trunc = trunc <8 x i16> %shift to <8 x i8>
ret <8 x i8> %trunc
}
-define <4 x i16> @vaddhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind {
+define <4 x i16> @vaddhni32_natural(<4 x i32> %A, <4 x i32> %B) {
; CHECK-LABEL: vaddhni32_natural:
-; CHECK: vaddhn.i32
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddhn.i32 d0, q0, q1
+; CHECK-NEXT: bx lr
%sum = add <4 x i32> %A, %B
%shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
%trunc = trunc <4 x i32> %shift to <4 x i16>
ret <4 x i16> %trunc
}
-define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind {
+define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) {
; CHECK-LABEL: vaddhni64_natural:
-; CHECK: vaddhn.i64
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddhn.i64 d0, q0, q1
+; CHECK-NEXT: bx lr
%sum = add <2 x i64> %A, %B
%shift = lshr <2 x i64> %sum, <i64 32, i64 32>
%trunc = trunc <2 x i64> %shift to <2 x i32>
ret <2 x i32> %trunc
}
-define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddls8:
-;CHECK: vaddl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddls16:
-;CHECK: vaddl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddls32:
-;CHECK: vaddl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddlu8:
-;CHECK: vaddl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddlu16:
-;CHECK: vaddl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddlu32:
-;CHECK: vaddl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddws8:
-;CHECK: vaddw.s8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = add <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddws16:
-;CHECK: vaddw.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = add <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddws32:
-;CHECK: vaddw.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = add <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddwu8:
-;CHECK: vaddw.u8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = add <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddwu16:
-;CHECK: vaddw.u16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = add <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddwu32:
-;CHECK: vaddw.u32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = add <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
+define <8 x i16> @vaddls8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddls8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddl.s8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <8 x i8> %A to <8 x i16>
+ %tmp4 = sext <8 x i8> %B to <8 x i16>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vaddls16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddls16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddl.s16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <4 x i16> %A to <4 x i32>
+ %tmp4 = sext <4 x i16> %B to <4 x i32>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vaddls32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddls32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddl.s32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <2 x i32> %A to <2 x i64>
+ %tmp4 = sext <2 x i32> %B to <2 x i64>
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vaddlu8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddlu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddl.u8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %A to <8 x i16>
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vaddlu16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddlu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddl.u16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %A to <4 x i32>
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vaddlu32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddlu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddl.u32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %A to <2 x i64>
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vaddla8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddla8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d1
+; CHECK-NEXT: vmovl.u8 q9, d0
+; CHECK-NEXT: vadd.i16 q0, q9, q8
+; CHECK-NEXT: vbic.i16 q0, #0xff00
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %A to <8 x i16>
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ ret <8 x i16> %and
+}
+
+define <4 x i32> @vaddla16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddla16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u16 q8, d1
+; CHECK-NEXT: vmovl.u16 q9, d0
+; CHECK-NEXT: vmov.i32 q10, #0xffff
+; CHECK-NEXT: vadd.i32 q8, q9, q8
+; CHECK-NEXT: vand q0, q8, q10
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %A to <4 x i32>
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define <2 x i64> @vaddla32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddla32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u32 q8, d1
+; CHECK-NEXT: vmovl.u32 q9, d0
+; CHECK-NEXT: vmov.i64 q10, #0xffffffff
+; CHECK-NEXT: vadd.i64 q8, q9, q8
+; CHECK-NEXT: vand q0, q8, q10
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %A to <2 x i64>
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
+}
+
+define <8 x i16> @vaddws8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddws8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddw.s8 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <8 x i8> %B to <8 x i16>
+ %tmp4 = add <8 x i16> %A, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vaddws16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddws16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddw.s16 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <4 x i16> %B to <4 x i32>
+ %tmp4 = add <4 x i32> %A, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vaddws32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddws32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddw.s32 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <2 x i32> %B to <2 x i64>
+ %tmp4 = add <2 x i64> %A, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vaddwu8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddwu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddw.u8 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %B to <8 x i16>
+ %tmp4 = add <8 x i16> %A, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vaddwu16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddwu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddw.u16 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %B to <4 x i32>
+ %tmp4 = add <4 x i32> %A, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vaddwu32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddwu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vaddw.u32 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %B to <2 x i64>
+ %tmp4 = add <2 x i64> %A, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vaddwa8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddwa8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d2
+; CHECK-NEXT: vadd.i16 q0, q0, q8
+; CHECK-NEXT: vbic.i16 q0, #0xff00
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %B to <8 x i16>
+ %tmp4 = add <8 x i16> %A, %tmp3
+ %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ ret <8 x i16> %and
+}
+
+define <4 x i32> @vaddwa16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddwa16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u16 q8, d2
+; CHECK-NEXT: vmov.i32 q9, #0xffff
+; CHECK-NEXT: vadd.i32 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %B to <4 x i32>
+ %tmp4 = add <4 x i32> %A, %tmp3
+ %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define <2 x i64> @vaddwa32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddwa32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u32 q8, d2
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: vadd.i64 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %B to <2 x i64>
+ %tmp4 = add <2 x i64> %A, %tmp3
+ %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
}
diff --git a/llvm/test/CodeGen/ARM/vmla.ll b/llvm/test/CodeGen/ARM/vmla.ll
index 8ca33a9eecac..14d425da2df4 100644
--- a/llvm/test/CodeGen/ARM/vmla.ll
+++ b/llvm/test/CodeGen/ARM/vmla.ll
@@ -1,175 +1,234 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlai8:
-;CHECK: vmla.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
- %tmp4 = mul <8 x i8> %tmp2, %tmp3
- %tmp5 = add <8 x i8> %tmp1, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlai16:
-;CHECK: vmla.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
- %tmp4 = mul <4 x i16> %tmp2, %tmp3
- %tmp5 = add <4 x i16> %tmp1, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlai32:
-;CHECK: vmla.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
- %tmp4 = mul <2 x i32> %tmp2, %tmp3
- %tmp5 = add <2 x i32> %tmp1, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: vmlaf32:
-;CHECK: vmla.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
- %tmp3 = load <2 x float>, <2 x float>* %C
- %tmp4 = fmul <2 x float> %tmp2, %tmp3
- %tmp5 = fadd <2 x float> %tmp1, %tmp4
- ret <2 x float> %tmp5
-}
-
-define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlaQi8:
-;CHECK: vmla.i8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <16 x i8>, <16 x i8>* %C
- %tmp4 = mul <16 x i8> %tmp2, %tmp3
- %tmp5 = add <16 x i8> %tmp1, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlaQi16:
-;CHECK: vmla.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
- %tmp4 = mul <8 x i16> %tmp2, %tmp3
- %tmp5 = add <8 x i16> %tmp1, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlaQi32:
-;CHECK: vmla.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
- %tmp4 = mul <4 x i32> %tmp2, %tmp3
- %tmp5 = add <4 x i32> %tmp1, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: vmlaQf32:
-;CHECK: vmla.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
- %tmp3 = load <4 x float>, <4 x float>* %C
- %tmp4 = fmul <4 x float> %tmp2, %tmp3
- %tmp5 = fadd <4 x float> %tmp1, %tmp4
- ret <4 x float> %tmp5
-}
-
-define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlals8:
-;CHECK: vmlal.s8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
- %tmp6 = mul <8 x i16> %tmp4, %tmp5
- %tmp7 = add <8 x i16> %tmp1, %tmp6
- ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlals16:
-;CHECK: vmlal.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
- %tmp6 = mul <4 x i32> %tmp4, %tmp5
- %tmp7 = add <4 x i32> %tmp1, %tmp6
- ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlals32:
-;CHECK: vmlal.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
- %tmp6 = mul <2 x i64> %tmp4, %tmp5
- %tmp7 = add <2 x i64> %tmp1, %tmp6
- ret <2 x i64> %tmp7
-}
-
-define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlalu8:
-;CHECK: vmlal.u8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
- %tmp6 = mul <8 x i16> %tmp4, %tmp5
- %tmp7 = add <8 x i16> %tmp1, %tmp6
- ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlalu16:
-;CHECK: vmlal.u16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
- %tmp6 = mul <4 x i32> %tmp4, %tmp5
- %tmp7 = add <4 x i32> %tmp1, %tmp6
- ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlalu32:
-;CHECK: vmlal.u32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
- %tmp6 = mul <2 x i64> %tmp4, %tmp5
- %tmp7 = add <2 x i64> %tmp1, %tmp6
- ret <2 x i64> %tmp7
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vmlai8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlai8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.i8 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <8 x i8> %B, %C
+ %tmp5 = add <8 x i8> %A, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vmlai16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlai16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.i16 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <4 x i16> %B, %C
+ %tmp5 = add <4 x i16> %A, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vmlai32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlai32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.i32 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <2 x i32> %B, %C
+ %tmp5 = add <2 x i32> %A, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vmlaf32(<2 x float> %A, <2 x float> %B, <2 x float> %C) nounwind {
+; CHECK-LABEL: vmlaf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.f32 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = fmul <2 x float> %B, %C
+ %tmp5 = fadd <2 x float> %A, %tmp4
+ ret <2 x float> %tmp5
+}
+
+define <16 x i8> @vmlaQi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) nounwind {
+; CHECK-LABEL: vmlaQi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.i8 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <16 x i8> %B, %C
+ %tmp5 = add <16 x i8> %A, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vmlaQi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) nounwind {
+; CHECK-LABEL: vmlaQi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.i16 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <8 x i16> %B, %C
+ %tmp5 = add <8 x i16> %A, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vmlaQi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) nounwind {
+; CHECK-LABEL: vmlaQi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.i32 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <4 x i32> %B, %C
+ %tmp5 = add <4 x i32> %A, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vmlaQf32(<4 x float> %A, <4 x float> %B, <4 x float> %C) nounwind {
+; CHECK-LABEL: vmlaQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmla.f32 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = fmul <4 x float> %B, %C
+ %tmp5 = fadd <4 x float> %A, %tmp4
+ ret <4 x float> %tmp5
+}
+
+define <8 x i16> @vmlals8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlals8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlal.s8 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = sext <8 x i8> %B to <8 x i16>
+ %tmp5 = sext <8 x i8> %C to <8 x i16>
+ %tmp6 = mul <8 x i16> %tmp4, %tmp5
+ %tmp7 = add <8 x i16> %A, %tmp6
+ ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlals16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlals16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlal.s16 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = sext <4 x i16> %B to <4 x i32>
+ %tmp5 = sext <4 x i16> %C to <4 x i32>
+ %tmp6 = mul <4 x i32> %tmp4, %tmp5
+ %tmp7 = add <4 x i32> %A, %tmp6
+ ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlals32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlals32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlal.s32 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = sext <2 x i32> %B to <2 x i64>
+ %tmp5 = sext <2 x i32> %C to <2 x i64>
+ %tmp6 = mul <2 x i64> %tmp4, %tmp5
+ %tmp7 = add <2 x i64> %A, %tmp6
+ ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlalu8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlalu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlal.u8 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = zext <8 x i8> %C to <8 x i16>
+ %tmp6 = mul <8 x i16> %tmp4, %tmp5
+ %tmp7 = add <8 x i16> %A, %tmp6
+ ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlalu16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlalu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlal.u16 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = zext <4 x i16> %C to <4 x i32>
+ %tmp6 = mul <4 x i32> %tmp4, %tmp5
+ %tmp7 = add <4 x i32> %A, %tmp6
+ ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlalu32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlalu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlal.u32 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = zext <2 x i32> %C to <2 x i64>
+ %tmp6 = mul <2 x i64> %tmp4, %tmp5
+ %tmp7 = add <2 x i64> %A, %tmp6
+ ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlala8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlala8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d3
+; CHECK-NEXT: vmovl.u8 q9, d2
+; CHECK-NEXT: vmla.i16 q0, q9, q8
+; CHECK-NEXT: vbic.i16 q0, #0xff00
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = zext <8 x i8> %C to <8 x i16>
+ %tmp6 = mul <8 x i16> %tmp4, %tmp5
+ %tmp7 = add <8 x i16> %A, %tmp6
+ %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ ret <8 x i16> %and
+}
+
+define <4 x i32> @vmlala16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlala16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u16 q8, d3
+; CHECK-NEXT: vmovl.u16 q9, d2
+; CHECK-NEXT: vmla.i32 q0, q9, q8
+; CHECK-NEXT: vmov.i32 q8, #0xffff
+; CHECK-NEXT: vand q0, q0, q8
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = zext <4 x i16> %C to <4 x i32>
+ %tmp6 = mul <4 x i32> %tmp4, %tmp5
+ %tmp7 = add <4 x i32> %A, %tmp6
+ %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define <2 x i64> @vmlala32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlala32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmovl.u32 q8, d3
+; CHECK-NEXT: vmovl.u32 q9, d2
+; CHECK-NEXT: vmov.32 r0, d16[0]
+; CHECK-NEXT: vmov.32 r1, d18[0]
+; CHECK-NEXT: vmov.32 r12, d16[1]
+; CHECK-NEXT: vmov.32 r3, d17[0]
+; CHECK-NEXT: vmov.32 r2, d19[0]
+; CHECK-NEXT: vmov.32 lr, d17[1]
+; CHECK-NEXT: vmov.32 r6, d19[1]
+; CHECK-NEXT: umull r7, r5, r1, r0
+; CHECK-NEXT: mla r1, r1, r12, r5
+; CHECK-NEXT: umull r5, r4, r2, r3
+; CHECK-NEXT: mla r2, r2, lr, r4
+; CHECK-NEXT: vmov.32 r4, d18[1]
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: mla r2, r6, r3, r2
+; CHECK-NEXT: vmov.32 d17[0], r5
+; CHECK-NEXT: vmov.32 d16[0], r7
+; CHECK-NEXT: vmov.32 d17[1], r2
+; CHECK-NEXT: mla r0, r4, r0, r1
+; CHECK-NEXT: vmov.32 d16[1], r0
+; CHECK-NEXT: vadd.i64 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = zext <2 x i32> %C to <2 x i64>
+ %tmp6 = mul <2 x i64> %tmp4, %tmp5
+ %tmp7 = add <2 x i64> %A, %tmp6
+ %and = and <2 x i64> %tmp7, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
}
define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanes16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlal.s16 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlal_lanes16
-; CHECK: vmlal.s16 q0, d2, d3[1]
%0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32>
%2 = sext <4 x i16> %0 to <4 x i32>
@@ -179,9 +238,11 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanes32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlal.s32 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlal_lanes32
-; CHECK: vmlal.s32 q0, d2, d3[1]
%0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64>
%2 = sext <2 x i32> %0 to <2 x i64>
@@ -191,9 +252,11 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vmlal_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_laneu16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlal.u16 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlal_laneu16
-; CHECK: vmlal.u16 q0, d2, d3[1]
%0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
%2 = zext <4 x i16> %0 to <4 x i32>
@@ -203,9 +266,11 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @test_vmlal_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_laneu32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlal.u32 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlal_laneu32
-; CHECK: vmlal.u32 q0, d2, d3[1]
%0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
%2 = zext <2 x i32> %0 to <2 x i64>
@@ -213,3 +278,63 @@ entry:
%4 = add <2 x i64> %arg0_uint64x2_t, %3
ret <2 x i64> %4
}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanea16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanea16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vdup.16 d16, d3[1]
+; CHECK-NEXT: vmovl.u16 q9, d2
+; CHECK-NEXT: vmovl.u16 q8, d16
+; CHECK-NEXT: vmla.i32 q0, q9, q8
+; CHECK-NEXT: vmov.i32 q8, #0xffff
+; CHECK-NEXT: vand q0, q0, q8
+; CHECK-NEXT: bx lr
+entry:
+ %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
+ %2 = zext <4 x i16> %0 to <4 x i32>
+ %3 = mul <4 x i32> %1, %2
+ %4 = add <4 x i32> %arg0_uint32x4_t, %3
+ %and = and <4 x i32> %4, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanea32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanea32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vdup.32 d16, d3[1]
+; CHECK-NEXT: vmovl.u32 q9, d2
+; CHECK-NEXT: vmovl.u32 q8, d16
+; CHECK-NEXT: vmov.32 r0, d18[0]
+; CHECK-NEXT: vmov.32 r3, d19[0]
+; CHECK-NEXT: vmov.32 r1, d16[0]
+; CHECK-NEXT: vmov.32 r12, d16[1]
+; CHECK-NEXT: vmov.32 r2, d17[0]
+; CHECK-NEXT: vmov.32 lr, d17[1]
+; CHECK-NEXT: vmov.32 r6, d19[1]
+; CHECK-NEXT: umull r7, r5, r0, r1
+; CHECK-NEXT: mla r0, r0, r12, r5
+; CHECK-NEXT: umull r5, r4, r3, r2
+; CHECK-NEXT: mla r3, r3, lr, r4
+; CHECK-NEXT: vmov.32 r4, d18[1]
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: mla r2, r6, r2, r3
+; CHECK-NEXT: vmov.32 d17[0], r5
+; CHECK-NEXT: vmov.32 d16[0], r7
+; CHECK-NEXT: vmov.32 d17[1], r2
+; CHECK-NEXT: mla r0, r4, r1, r0
+; CHECK-NEXT: vmov.32 d16[1], r0
+; CHECK-NEXT: vadd.i64 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+entry:
+ %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
+ %2 = zext <2 x i32> %0 to <2 x i64>
+ %3 = mul <2 x i64> %1, %2
+ %4 = add <2 x i64> %arg0_uint64x2_t, %3
+ %and = and <2 x i64> %4, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
+}
diff --git a/llvm/test/CodeGen/ARM/vmls.ll b/llvm/test/CodeGen/ARM/vmls.ll
index d14928147a36..eef90041b96f 100644
--- a/llvm/test/CodeGen/ARM/vmls.ll
+++ b/llvm/test/CodeGen/ARM/vmls.ll
@@ -1,175 +1,234 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlsi8:
-;CHECK: vmls.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
- %tmp4 = mul <8 x i8> %tmp2, %tmp3
- %tmp5 = sub <8 x i8> %tmp1, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlsi16:
-;CHECK: vmls.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
- %tmp4 = mul <4 x i16> %tmp2, %tmp3
- %tmp5 = sub <4 x i16> %tmp1, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlsi32:
-;CHECK: vmls.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
- %tmp4 = mul <2 x i32> %tmp2, %tmp3
- %tmp5 = sub <2 x i32> %tmp1, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: vmlsf32:
-;CHECK: vmls.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
- %tmp3 = load <2 x float>, <2 x float>* %C
- %tmp4 = fmul <2 x float> %tmp2, %tmp3
- %tmp5 = fsub <2 x float> %tmp1, %tmp4
- ret <2 x float> %tmp5
-}
-
-define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlsQi8:
-;CHECK: vmls.i8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <16 x i8>, <16 x i8>* %C
- %tmp4 = mul <16 x i8> %tmp2, %tmp3
- %tmp5 = sub <16 x i8> %tmp1, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlsQi16:
-;CHECK: vmls.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
- %tmp4 = mul <8 x i16> %tmp2, %tmp3
- %tmp5 = sub <8 x i16> %tmp1, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlsQi32:
-;CHECK: vmls.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
- %tmp4 = mul <4 x i32> %tmp2, %tmp3
- %tmp5 = sub <4 x i32> %tmp1, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: vmlsQf32:
-;CHECK: vmls.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
- %tmp3 = load <4 x float>, <4 x float>* %C
- %tmp4 = fmul <4 x float> %tmp2, %tmp3
- %tmp5 = fsub <4 x float> %tmp1, %tmp4
- ret <4 x float> %tmp5
-}
-
-define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlsls8:
-;CHECK: vmlsl.s8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
- %tmp6 = mul <8 x i16> %tmp4, %tmp5
- %tmp7 = sub <8 x i16> %tmp1, %tmp6
- ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlsls16:
-;CHECK: vmlsl.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
- %tmp6 = mul <4 x i32> %tmp4, %tmp5
- %tmp7 = sub <4 x i32> %tmp1, %tmp6
- ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlsls32:
-;CHECK: vmlsl.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
- %tmp6 = mul <2 x i64> %tmp4, %tmp5
- %tmp7 = sub <2 x i64> %tmp1, %tmp6
- ret <2 x i64> %tmp7
-}
-
-define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlslu8:
-;CHECK: vmlsl.u8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
- %tmp6 = mul <8 x i16> %tmp4, %tmp5
- %tmp7 = sub <8 x i16> %tmp1, %tmp6
- ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlslu16:
-;CHECK: vmlsl.u16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
- %tmp6 = mul <4 x i32> %tmp4, %tmp5
- %tmp7 = sub <4 x i32> %tmp1, %tmp6
- ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlslu32:
-;CHECK: vmlsl.u32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
- %tmp6 = mul <2 x i64> %tmp4, %tmp5
- %tmp7 = sub <2 x i64> %tmp1, %tmp6
- ret <2 x i64> %tmp7
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vmlsi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlsi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.i8 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <8 x i8> %B, %C
+ %tmp5 = sub <8 x i8> %A, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vmlsi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.i16 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <4 x i16> %B, %C
+ %tmp5 = sub <4 x i16> %A, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vmlsi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.i32 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <2 x i32> %B, %C
+ %tmp5 = sub <2 x i32> %A, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vmlsf32(<2 x float> %A, <2 x float> %B, <2 x float> %C) nounwind {
+; CHECK-LABEL: vmlsf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.f32 d0, d1, d2
+; CHECK-NEXT: bx lr
+ %tmp4 = fmul <2 x float> %B, %C
+ %tmp5 = fsub <2 x float> %A, %tmp4
+ ret <2 x float> %tmp5
+}
+
+define <16 x i8> @vmlsQi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) nounwind {
+; CHECK-LABEL: vmlsQi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.i8 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <16 x i8> %B, %C
+ %tmp5 = sub <16 x i8> %A, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vmlsQi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsQi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.i16 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <8 x i16> %B, %C
+ %tmp5 = sub <8 x i16> %A, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vmlsQi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsQi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.i32 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = mul <4 x i32> %B, %C
+ %tmp5 = sub <4 x i32> %A, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vmlsQf32(<4 x float> %A, <4 x float> %B, <4 x float> %C) nounwind {
+; CHECK-LABEL: vmlsQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmls.f32 q0, q1, q2
+; CHECK-NEXT: bx lr
+ %tmp4 = fmul <4 x float> %B, %C
+ %tmp5 = fsub <4 x float> %A, %tmp4
+ ret <4 x float> %tmp5
+}
+
+define <8 x i16> @vmlsls8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlsls8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlsl.s8 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = sext <8 x i8> %B to <8 x i16>
+ %tmp5 = sext <8 x i8> %C to <8 x i16>
+ %tmp6 = mul <8 x i16> %tmp4, %tmp5
+ %tmp7 = sub <8 x i16> %A, %tmp6
+ ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlsls16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsls16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlsl.s16 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = sext <4 x i16> %B to <4 x i32>
+ %tmp5 = sext <4 x i16> %C to <4 x i32>
+ %tmp6 = mul <4 x i32> %tmp4, %tmp5
+ %tmp7 = sub <4 x i32> %A, %tmp6
+ ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlsls32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsls32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlsl.s32 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = sext <2 x i32> %B to <2 x i64>
+ %tmp5 = sext <2 x i32> %C to <2 x i64>
+ %tmp6 = mul <2 x i64> %tmp4, %tmp5
+ %tmp7 = sub <2 x i64> %A, %tmp6
+ ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlslu8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlslu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlsl.u8 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = zext <8 x i8> %C to <8 x i16>
+ %tmp6 = mul <8 x i16> %tmp4, %tmp5
+ %tmp7 = sub <8 x i16> %A, %tmp6
+ ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlslu16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlslu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlsl.u16 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = zext <4 x i16> %C to <4 x i32>
+ %tmp6 = mul <4 x i32> %tmp4, %tmp5
+ %tmp7 = sub <4 x i32> %A, %tmp6
+ ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlslu32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlslu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmlsl.u32 q0, d2, d3
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = zext <2 x i32> %C to <2 x i64>
+ %tmp6 = mul <2 x i64> %tmp4, %tmp5
+ %tmp7 = sub <2 x i64> %A, %tmp6
+ ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlsla8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlsla8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d3
+; CHECK-NEXT: vmovl.u8 q9, d2
+; CHECK-NEXT: vmls.i16 q0, q9, q8
+; CHECK-NEXT: vbic.i16 q0, #0xff00
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = zext <8 x i8> %C to <8 x i16>
+ %tmp6 = mul <8 x i16> %tmp4, %tmp5
+ %tmp7 = sub <8 x i16> %A, %tmp6
+ %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ ret <8 x i16> %and
+}
+
+define <4 x i32> @vmlsla16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsla16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u16 q8, d3
+; CHECK-NEXT: vmovl.u16 q9, d2
+; CHECK-NEXT: vmls.i32 q0, q9, q8
+; CHECK-NEXT: vmov.i32 q8, #0xffff
+; CHECK-NEXT: vand q0, q0, q8
+; CHECK-NEXT: bx lr
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = zext <4 x i16> %C to <4 x i32>
+ %tmp6 = mul <4 x i32> %tmp4, %tmp5
+ %tmp7 = sub <4 x i32> %A, %tmp6
+ %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define <2 x i64> @vmlsla32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsla32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmovl.u32 q8, d3
+; CHECK-NEXT: vmovl.u32 q9, d2
+; CHECK-NEXT: vmov.32 r0, d16[0]
+; CHECK-NEXT: vmov.32 r1, d18[0]
+; CHECK-NEXT: vmov.32 r12, d16[1]
+; CHECK-NEXT: vmov.32 r3, d17[0]
+; CHECK-NEXT: vmov.32 r2, d19[0]
+; CHECK-NEXT: vmov.32 lr, d17[1]
+; CHECK-NEXT: vmov.32 r6, d19[1]
+; CHECK-NEXT: umull r7, r5, r1, r0
+; CHECK-NEXT: mla r1, r1, r12, r5
+; CHECK-NEXT: umull r5, r4, r2, r3
+; CHECK-NEXT: mla r2, r2, lr, r4
+; CHECK-NEXT: vmov.32 r4, d18[1]
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: mla r2, r6, r3, r2
+; CHECK-NEXT: vmov.32 d17[0], r5
+; CHECK-NEXT: vmov.32 d16[0], r7
+; CHECK-NEXT: vmov.32 d17[1], r2
+; CHECK-NEXT: mla r0, r4, r0, r1
+; CHECK-NEXT: vmov.32 d16[1], r0
+; CHECK-NEXT: vsub.i64 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = zext <2 x i32> %C to <2 x i64>
+ %tmp6 = mul <2 x i64> %tmp4, %tmp5
+ %tmp7 = sub <2 x i64> %A, %tmp6
+ %and = and <2 x i64> %tmp7, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
}
define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanes16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlsl.s16 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlsl_lanes16
-; CHECK: vmlsl.s16 q0, d2, d3[1]
%0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32>
%2 = sext <4 x i16> %0 to <4 x i32>
@@ -179,9 +238,11 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanes32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlsl.s32 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlsl_lanes32
-; CHECK: vmlsl.s32 q0, d2, d3[1]
%0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64>
%2 = sext <2 x i32> %0 to <2 x i64>
@@ -191,9 +252,11 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_laneu16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlsl.u16 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlsl_laneu16
-; CHECK: vmlsl.u16 q0, d2, d3[1]
%0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
%2 = zext <4 x i16> %0 to <4 x i32>
@@ -203,9 +266,11 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_laneu32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmlsl.u32 q0, d2, d3[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmlsl_laneu32
-; CHECK: vmlsl.u32 q0, d2, d3[1]
%0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
%2 = zext <2 x i32> %0 to <2 x i64>
@@ -213,3 +278,63 @@ entry:
%4 = sub <2 x i64> %arg0_uint64x2_t, %3
ret <2 x i64> %4
}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanea16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanea16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vdup.16 d16, d3[1]
+; CHECK-NEXT: vmovl.u16 q9, d2
+; CHECK-NEXT: vmovl.u16 q8, d16
+; CHECK-NEXT: vmls.i32 q0, q9, q8
+; CHECK-NEXT: vmov.i32 q8, #0xffff
+; CHECK-NEXT: vand q0, q0, q8
+; CHECK-NEXT: bx lr
+entry:
+ %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
+ %2 = zext <4 x i16> %0 to <4 x i32>
+ %3 = mul <4 x i32> %1, %2
+ %4 = sub <4 x i32> %arg0_uint32x4_t, %3
+ %and = and <4 x i32> %4, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanea32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanea32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vdup.32 d16, d3[1]
+; CHECK-NEXT: vmovl.u32 q9, d2
+; CHECK-NEXT: vmovl.u32 q8, d16
+; CHECK-NEXT: vmov.32 r0, d18[0]
+; CHECK-NEXT: vmov.32 r3, d19[0]
+; CHECK-NEXT: vmov.32 r1, d16[0]
+; CHECK-NEXT: vmov.32 r12, d16[1]
+; CHECK-NEXT: vmov.32 r2, d17[0]
+; CHECK-NEXT: vmov.32 lr, d17[1]
+; CHECK-NEXT: vmov.32 r6, d19[1]
+; CHECK-NEXT: umull r7, r5, r0, r1
+; CHECK-NEXT: mla r0, r0, r12, r5
+; CHECK-NEXT: umull r5, r4, r3, r2
+; CHECK-NEXT: mla r3, r3, lr, r4
+; CHECK-NEXT: vmov.32 r4, d18[1]
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: mla r2, r6, r2, r3
+; CHECK-NEXT: vmov.32 d17[0], r5
+; CHECK-NEXT: vmov.32 d16[0], r7
+; CHECK-NEXT: vmov.32 d17[1], r2
+; CHECK-NEXT: mla r0, r4, r1, r0
+; CHECK-NEXT: vmov.32 d16[1], r0
+; CHECK-NEXT: vsub.i64 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+entry:
+ %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
+ %2 = zext <2 x i32> %0 to <2 x i64>
+ %3 = mul <2 x i64> %1, %2
+ %4 = sub <2 x i64> %arg0_uint64x2_t, %3
+ %and = and <2 x i64> %4, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
+}
diff --git a/llvm/test/CodeGen/ARM/vmul.ll b/llvm/test/CodeGen/ARM/vmul.ll
index e8cf8d9b27b6..c57ace2a6c67 100644
--- a/llvm/test/CodeGen/ARM/vmul.ll
+++ b/llvm/test/CodeGen/ARM/vmul.ll
@@ -1,92 +1,93 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
-
-define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmuli8:
-;CHECK: vmul.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = mul <8 x i8> %tmp1, %tmp2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vmuli8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmuli8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.i8 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = mul <8 x i8> %A, %B
ret <8 x i8> %tmp3
}
-define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmuli16:
-;CHECK: vmul.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = mul <4 x i16> %tmp1, %tmp2
+define <4 x i16> @vmuli16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmuli16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.i16 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = mul <4 x i16> %A, %B
ret <4 x i16> %tmp3
}
-define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmuli32:
-;CHECK: vmul.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = mul <2 x i32> %tmp1, %tmp2
+define <2 x i32> @vmuli32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmuli32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.i32 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = mul <2 x i32> %A, %B
ret <2 x i32> %tmp3
}
-define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vmulf32:
-;CHECK: vmul.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
- %tmp3 = fmul <2 x float> %tmp1, %tmp2
+define <2 x float> @vmulf32(<2 x float> %A, <2 x float> %B) nounwind {
+; CHECK-LABEL: vmulf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.f32 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = fmul <2 x float> %A, %B
ret <2 x float> %tmp3
}
-define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulp8:
-;CHECK: vmul.p8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i8> @vmulp8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulp8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.p8 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %A, <8 x i8> %B)
ret <8 x i8> %tmp3
}
-define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulQi8:
-;CHECK: vmul.i8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = mul <16 x i8> %tmp1, %tmp2
+define <16 x i8> @vmulQi8(<16 x i8> %A, <16 x i8> %B) nounwind {
+; CHECK-LABEL: vmulQi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.i8 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = mul <16 x i8> %A, %B
ret <16 x i8> %tmp3
}
-define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vmulQi16:
-;CHECK: vmul.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = mul <8 x i16> %tmp1, %tmp2
+define <8 x i16> @vmulQi16(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK-LABEL: vmulQi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.i16 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = mul <8 x i16> %A, %B
ret <8 x i16> %tmp3
}
-define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vmulQi32:
-;CHECK: vmul.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = mul <4 x i32> %tmp1, %tmp2
+define <4 x i32> @vmulQi32(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK-LABEL: vmulQi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.i32 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = mul <4 x i32> %A, %B
ret <4 x i32> %tmp3
}
-define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vmulQf32:
-;CHECK: vmul.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
- %tmp3 = fmul <4 x float> %tmp1, %tmp2
+define <4 x float> @vmulQf32(<4 x float> %A, <4 x float> %B) nounwind {
+; CHECK-LABEL: vmulQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.f32 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = fmul <4 x float> %A, %B
ret <4 x float> %tmp3
}
-define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulQp8:
-;CHECK: vmul.p8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+define <16 x i8> @vmulQp8(<16 x i8> %A, <16 x i8> %B) nounwind {
+; CHECK-LABEL: vmulQp8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmul.p8 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %A, <16 x i8> %B)
ret <16 x i8> %tmp3
}
@@ -94,192 +95,275 @@ declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>) nounwind readnon
declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
-entry:
; CHECK-LABEL: test_vmul_lanef32:
-; CHECK: vmul.f32 d0, d0, d1[0]
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmul.f32 d0, d0, d1[0]
+; CHECK-NEXT: bx lr
+entry:
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
%1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1]
ret <2 x float> %1
}
define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
-entry:
; CHECK-LABEL: test_vmul_lanes16:
-; CHECK: vmul.i16 d0, d0, d1[1]
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmul.i16 d0, d0, d1[1]
+; CHECK-NEXT: bx lr
+entry:
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
%1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1]
ret <4 x i16> %1
}
define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
-entry:
; CHECK-LABEL: test_vmul_lanes32:
-; CHECK: vmul.i32 d0, d0, d1[1]
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmul.i32 d0, d0, d1[1]
+; CHECK-NEXT: bx lr
+entry:
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1]
ret <2 x i32> %1
}
define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
-entry:
; CHECK-LABEL: test_vmulQ_lanef32:
-; CHECK: vmul.f32 q0, q0, d2[1]
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: @ kill: def $d2 killed $d2 def $q1
+; CHECK-NEXT: vmul.f32 q0, q0, d2[1]
+; CHECK-NEXT: bx lr
+entry:
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
%1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1]
ret <4 x float> %1
}
define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
-entry:
; CHECK-LABEL: test_vmulQ_lanes16:
-; CHECK: vmul.i16 q0, q0, d2[1]
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: @ kill: def $d2 killed $d2 def $q1
+; CHECK-NEXT: vmul.i16 q0, q0, d2[1]
+; CHECK-NEXT: bx lr
+entry:
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1]
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
-entry:
; CHECK-LABEL: test_vmulQ_lanes32:
-; CHECK: vmul.i32 q0, q0, d2[1]
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: @ kill: def $d2 killed $d2 def $q1
+; CHECK-NEXT: vmul.i32 q0, q0, d2[1]
+; CHECK-NEXT: bx lr
+entry:
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
%1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1]
ret <4 x i32> %1
}
-define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulls8:
-;CHECK: vmull.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
+define <8 x i16> @vmulls8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulls8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.s8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <8 x i8> %A to <8 x i16>
+ %tmp4 = sext <8 x i8> %B to <8 x i16>
%tmp5 = mul <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
-define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulls8_int:
-;CHECK: vmull.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i16> @vmulls8_int(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulls8_int:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.s8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %A, <8 x i8> %B)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmulls16:
-;CHECK: vmull.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+define <4 x i32> @vmulls16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmulls16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.s16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <4 x i16> %A to <4 x i32>
+ %tmp4 = sext <4 x i16> %B to <4 x i32>
%tmp5 = mul <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
-define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmulls16_int:
-;CHECK: vmull.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+define <4 x i32> @vmulls16_int(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmulls16_int:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.s16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %A, <4 x i16> %B)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmulls32:
-;CHECK: vmull.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+define <2 x i64> @vmulls32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmulls32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.s32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <2 x i32> %A to <2 x i64>
+ %tmp4 = sext <2 x i32> %B to <2 x i64>
%tmp5 = mul <2 x i64> %tmp3, %tmp4
ret <2 x i64> %tmp5
}
-define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmulls32_int:
-;CHECK: vmull.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+define <2 x i64> @vmulls32_int(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmulls32_int:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.s32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %A, <2 x i32> %B)
ret <2 x i64> %tmp3
}
-define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmullu8:
-;CHECK: vmull.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+define <8 x i16> @vmullu8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmullu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.u8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %A to <8 x i16>
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
%tmp5 = mul <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
-define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmullu8_int:
-;CHECK: vmull.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i16> @vmullu8_int(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmullu8_int:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.u8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %A, <8 x i8> %B)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmullu16:
-;CHECK: vmull.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+define <4 x i32> @vmullu16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmullu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.u16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %A to <4 x i32>
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
%tmp5 = mul <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
-define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmullu16_int:
-;CHECK: vmull.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+define <4 x i32> @vmullu16_int(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmullu16_int:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.u16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %A, <4 x i16> %B)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmullu32:
-;CHECK: vmull.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+define <2 x i64> @vmullu32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmullu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.u32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %A to <2 x i64>
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
%tmp5 = mul <2 x i64> %tmp3, %tmp4
ret <2 x i64> %tmp5
}
-define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmullu32_int:
-;CHECK: vmull.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+define <2 x i64> @vmullu32_int(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmullu32_int:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.u32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %A, <2 x i32> %B)
ret <2 x i64> %tmp3
}
-define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmullp8:
-;CHECK: vmull.p8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i16> @vmulla8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulla8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d1
+; CHECK-NEXT: vmovl.u8 q9, d0
+; CHECK-NEXT: vmul.i16 q0, q9, q8
+; CHECK-NEXT: vbic.i16 q0, #0xff00
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %A to <8 x i16>
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = mul <8 x i16> %tmp3, %tmp4
+ %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ ret <8 x i16> %and
+}
+
+define <4 x i32> @vmulla16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmulla16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u16 q8, d1
+; CHECK-NEXT: vmovl.u16 q9, d0
+; CHECK-NEXT: vmul.i32 q8, q9, q8
+; CHECK-NEXT: vmov.i32 q9, #0xffff
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %A to <4 x i32>
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = mul <4 x i32> %tmp3, %tmp4
+ %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define <2 x i64> @vmulla32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmulla32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmovl.u32 q8, d1
+; CHECK-NEXT: vmovl.u32 q9, d0
+; CHECK-NEXT: vmov.32 r0, d16[0]
+; CHECK-NEXT: vmov.32 r1, d18[0]
+; CHECK-NEXT: vmov.32 r12, d16[1]
+; CHECK-NEXT: vmov.32 r3, d17[0]
+; CHECK-NEXT: vmov.32 r2, d19[0]
+; CHECK-NEXT: vmov.32 lr, d17[1]
+; CHECK-NEXT: vmov.32 r6, d19[1]
+; CHECK-NEXT: umull r7, r5, r1, r0
+; CHECK-NEXT: mla r1, r1, r12, r5
+; CHECK-NEXT: umull r5, r4, r2, r3
+; CHECK-NEXT: mla r2, r2, lr, r4
+; CHECK-NEXT: vmov.32 r4, d18[1]
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: mla r2, r6, r3, r2
+; CHECK-NEXT: vmov.32 d17[0], r5
+; CHECK-NEXT: vmov.32 d16[0], r7
+; CHECK-NEXT: vmov.32 d17[1], r2
+; CHECK-NEXT: mla r0, r4, r0, r1
+; CHECK-NEXT: vmov.32 d16[1], r0
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %tmp3 = zext <2 x i32> %A to <2 x i64>
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = mul <2 x i64> %tmp3, %tmp4
+ %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
+}
+
+define <8 x i16> @vmullp8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmullp8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmull.p8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %A, <8 x i8> %B)
ret <8 x i16> %tmp3
}
define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.s16 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_lanes16
-; CHECK: vmull.s16 q0, d0, d1[1]
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = sext <4 x i16> %arg0_int16x4_t to <4 x i32>
%2 = sext <4 x i16> %0 to <4 x i32>
@@ -288,18 +372,22 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16_int(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes16_int:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.s16 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_lanes16_int
-; CHECK: vmull.s16 q0, d0, d1[1]
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.s32 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_lanes32
-; CHECK: vmull.s32 q0, d0, d1[1]
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = sext <2 x i32> %arg0_int32x2_t to <2 x i64>
%2 = sext <2 x i32> %0 to <2 x i64>
@@ -308,18 +396,22 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32_int(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes32_int:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.s32 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_lanes32_int
-; CHECK: vmull.s32 q0, d0, d1[1]
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %1
}
define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.u16 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_laneu16
-; CHECK: vmull.u16 q0, d0, d1[1]
%0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32>
%2 = zext <4 x i16> %0 to <4 x i32>
@@ -328,18 +420,22 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16_int(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu16_int:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.u16 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_laneu16_int
-; CHECK: vmull.u16 q0, d0, d1[1]
%0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
%1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.u32 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_laneu32
-; CHECK: vmull.u32 q0, d0, d1[1]
%0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64>
%2 = zext <2 x i32> %0 to <2 x i64>
@@ -348,14 +444,73 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32_int(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu32_int:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmull.u32 q0, d0, d1[1]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: test_vmull_laneu32_int
-; CHECK: vmull.u32 q0, d0, d1[1]
%0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %1
}
+define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanea16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanea16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vdup.16 d16, d1[1]
+; CHECK-NEXT: vmovl.u16 q9, d0
+; CHECK-NEXT: vmovl.u16 q8, d16
+; CHECK-NEXT: vmul.i32 q8, q9, q8
+; CHECK-NEXT: vmov.i32 q9, #0xffff
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: bx lr
+entry:
+ %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32>
+ %2 = zext <4 x i16> %0 to <4 x i32>
+ %3 = mul <4 x i32> %1, %2
+ %and = and <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanea32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanea32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vdup.32 d16, d1[1]
+; CHECK-NEXT: vmovl.u32 q9, d0
+; CHECK-NEXT: vmovl.u32 q8, d16
+; CHECK-NEXT: vmov.32 r0, d18[0]
+; CHECK-NEXT: vmov.32 r3, d19[0]
+; CHECK-NEXT: vmov.32 r1, d16[0]
+; CHECK-NEXT: vmov.32 r12, d16[1]
+; CHECK-NEXT: vmov.32 r2, d17[0]
+; CHECK-NEXT: vmov.32 lr, d17[1]
+; CHECK-NEXT: vmov.32 r6, d19[1]
+; CHECK-NEXT: umull r7, r5, r0, r1
+; CHECK-NEXT: mla r0, r0, r12, r5
+; CHECK-NEXT: umull r5, r4, r3, r2
+; CHECK-NEXT: mla r3, r3, lr, r4
+; CHECK-NEXT: vmov.32 r4, d18[1]
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: mla r2, r6, r2, r3
+; CHECK-NEXT: vmov.32 d17[0], r5
+; CHECK-NEXT: vmov.32 d16[0], r7
+; CHECK-NEXT: vmov.32 d17[1], r2
+; CHECK-NEXT: mla r0, r4, r1, r0
+; CHECK-NEXT: vmov.32 d16[1], r0
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+entry:
+ %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64>
+ %2 = zext <2 x i32> %0 to <2 x i64>
+ %3 = mul <2 x i64> %1, %2
+ %and = and <2 x i64> %3, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
+}
+
declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
@@ -371,16 +526,22 @@ declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind read
; VMULL needs to recognize BUILD_VECTORs with sign/zero-extended elements.
define <8 x i16> @vmull_extvec_s8(<8 x i8> %arg) nounwind {
-; CHECK: vmull_extvec_s8
-; CHECK: vmull.s8
+; CHECK-LABEL: vmull_extvec_s8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.i8 d16, #0xf4
+; CHECK-NEXT: vmull.s8 q0, d0, d16
+; CHECK-NEXT: bx lr
%tmp3 = sext <8 x i8> %arg to <8 x i16>
%tmp4 = mul <8 x i16> %tmp3, <i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12>
ret <8 x i16> %tmp4
}
define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind {
-; CHECK: vmull_extvec_u8
-; CHECK: vmull.u8
+; CHECK-LABEL: vmull_extvec_u8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.i8 d16, #0xc
+; CHECK-NEXT: vmull.u8 q0, d0, d16
+; CHECK-NEXT: bx lr
%tmp3 = zext <8 x i8> %arg to <8 x i16>
%tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
ret <8 x i16> %tmp4
@@ -388,9 +549,24 @@ define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind {
define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind {
; Do not use VMULL if the BUILD_VECTOR element values are too big.
-; CHECK: vmull_noextvec_s8
-; CHECK: vmovl.s8
-; CHECK: vmul.i16
+; CHECK-LABEL: vmull_noextvec_s8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.s8 q8, d0
+; CHECK-NEXT: adr r0, .LCPI44_0
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: vmul.i16 q0, q8, q9
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI44_0:
+; CHECK-NEXT: .short 64537 @ 0xfc19
+; CHECK-NEXT: .short 64537 @ 0xfc19
+; CHECK-NEXT: .short 64537 @ 0xfc19
+; CHECK-NEXT: .short 64537 @ 0xfc19
+; CHECK-NEXT: .short 64537 @ 0xfc19
+; CHECK-NEXT: .short 64537 @ 0xfc19
+; CHECK-NEXT: .short 64537 @ 0xfc19
+; CHECK-NEXT: .short 64537 @ 0xfc19
%tmp3 = sext <8 x i8> %arg to <8 x i16>
%tmp4 = mul <8 x i16> %tmp3, <i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999>
ret <8 x i16> %tmp4
@@ -398,41 +574,85 @@ define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind {
define <8 x i16> @vmull_noextvec_u8(<8 x i8> %arg) nounwind {
; Do not use VMULL if the BUILD_VECTOR element values are too big.
-; CHECK: vmull_noextvec_u8
-; CHECK: vmovl.u8
-; CHECK: vmul.i16
+; CHECK-LABEL: vmull_noextvec_u8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d0
+; CHECK-NEXT: adr r0, .LCPI45_0
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: vmul.i16 q0, q8, q9
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI45_0:
+; CHECK-NEXT: .short 999 @ 0x3e7
+; CHECK-NEXT: .short 999 @ 0x3e7
+; CHECK-NEXT: .short 999 @ 0x3e7
+; CHECK-NEXT: .short 999 @ 0x3e7
+; CHECK-NEXT: .short 999 @ 0x3e7
+; CHECK-NEXT: .short 999 @ 0x3e7
+; CHECK-NEXT: .short 999 @ 0x3e7
+; CHECK-NEXT: .short 999 @ 0x3e7
%tmp3 = zext <8 x i8> %arg to <8 x i16>
%tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>
ret <8 x i16> %tmp4
}
define <4 x i32> @vmull_extvec_s16(<4 x i16> %arg) nounwind {
-; CHECK: vmull_extvec_s16
-; CHECK: vmull.s16
+; CHECK-LABEL: vmull_extvec_s16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmvn.i16 d16, #0xb
+; CHECK-NEXT: vmull.s16 q0, d0, d16
+; CHECK-NEXT: bx lr
%tmp3 = sext <4 x i16> %arg to <4 x i32>
%tmp4 = mul <4 x i32> %tmp3, <i32 -12, i32 -12, i32 -12, i32 -12>
ret <4 x i32> %tmp4
}
define <4 x i32> @vmull_extvec_u16(<4 x i16> %arg) nounwind {
-; CHECK: vmull_extvec_u16
-; CHECK: vmull.u16
+; CHECK-LABEL: vmull_extvec_u16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, .LCPI47_0
+; CHECK-NEXT: vmull.u16 q0, d0, d16
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI47_0:
+; CHECK-NEXT: .short 1234 @ 0x4d2
+; CHECK-NEXT: .short 1234 @ 0x4d2
+; CHECK-NEXT: .short 1234 @ 0x4d2
+; CHECK-NEXT: .short 1234 @ 0x4d2
%tmp3 = zext <4 x i16> %arg to <4 x i32>
%tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
ret <4 x i32> %tmp4
}
define <2 x i64> @vmull_extvec_s32(<2 x i32> %arg) nounwind {
-; CHECK: vmull_extvec_s32
-; CHECK: vmull.s32
+; CHECK-LABEL: vmull_extvec_s32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, .LCPI48_0
+; CHECK-NEXT: vmull.s32 q0, d0, d16
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI48_0:
+; CHECK-NEXT: .long 4294966062 @ 0xfffffb2e
+; CHECK-NEXT: .long 4294966062 @ 0xfffffb2e
%tmp3 = sext <2 x i32> %arg to <2 x i64>
%tmp4 = mul <2 x i64> %tmp3, <i64 -1234, i64 -1234>
ret <2 x i64> %tmp4
}
define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
-; CHECK: vmull_extvec_u32
-; CHECK: vmull.u32
+; CHECK-LABEL: vmull_extvec_u32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, .LCPI49_0
+; CHECK-NEXT: vmull.u32 q0, d0, d16
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI49_0:
+; CHECK-NEXT: .long 1234 @ 0x4d2
+; CHECK-NEXT: .long 1234 @ 0x4d2
%tmp3 = zext <2 x i32> %arg to <2 x i64>
%tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
ret <2 x i64> %tmp4
@@ -440,10 +660,15 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
; rdar://9197392
define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
-entry:
; CHECK-LABEL: distribute:
-; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]]
-; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]]
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld1.8 {d16, d17}, [r1]
+; CHECK-NEXT: vdup.8 d18, r2
+; CHECK-NEXT: vmull.u8 q10, d17, d18
+; CHECK-NEXT: vmlal.u8 q10, d16, d18
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0]
+; CHECK-NEXT: bx lr
+entry:
%0 = trunc i32 %mul to i8
%1 = insertelement <8 x i8> undef, i8 %0, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -472,11 +697,15 @@ declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
%struct.uint8x8_t = type { <8 x i8> }
define void @distribute2(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind {
+; CHECK-LABEL: distribute2:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld1.8 {d16, d17}, [r1]
+; CHECK-NEXT: vadd.i8 d16, d17, d16
+; CHECK-NEXT: vdup.8 d17, r2
+; CHECK-NEXT: vmul.i8 d16, d16, d17
+; CHECK-NEXT: vstr d16, [r0]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: distribute2
-; CHECK-NOT: vadd.i8
-; CHECK: vmul.i8
-; CHECK: vmla.i8
%0 = trunc i32 %mul to i8
%1 = insertelement <8 x i8> undef, i8 %0, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -494,11 +723,15 @@ entry:
}
define void @distribute2_commutative(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind {
+; CHECK-LABEL: distribute2_commutative:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld1.8 {d16, d17}, [r1]
+; CHECK-NEXT: vadd.i8 d16, d17, d16
+; CHECK-NEXT: vdup.8 d17, r2
+; CHECK-NEXT: vmul.i8 d16, d17, d16
+; CHECK-NEXT: vstr d16, [r0]
+; CHECK-NEXT: bx lr
entry:
-; CHECK: distribute2_commutative
-; CHECK-NOT: vadd.i8
-; CHECK: vmul.i8
-; CHECK: vmla.i8
%0 = trunc i32 %mul to i8
%1 = insertelement <8 x i8> undef, i8 %0, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -516,11 +749,12 @@ entry:
}
define <8 x i8> @no_distribute(<8 x i8> %a, <8 x i8> %b) nounwind {
+; CHECK-LABEL: no_distribute:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vadd.i8 d16, d0, d1
+; CHECK-NEXT: vmul.i8 d0, d16, d16
+; CHECK-NEXT: bx lr
entry:
-; CHECK: no_distribute
-; CHECK: vadd.i8
-; CHECK: vmul.i8
-; CHECK-NOT: vmla.i8
%0 = add <8 x i8> %a, %b
%1 = mul <8x i8> %0, %0
ret <8 x i8> %1
@@ -529,8 +763,13 @@ entry:
; If one operand has a zero-extend and the other a sign-extend, vmull
; cannot be used.
define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
-; CHECK: vmullWithInconsistentExtensions
-; CHECK-NOT: vmull.s8
+; CHECK-LABEL: vmullWithInconsistentExtensions:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.s8 q8, d0
+; CHECK-NEXT: vmov.i16 q9, #0xff
+; CHECK-NEXT: vmul.i16 q8, q8, q9
+; CHECK-NEXT: vmov.u16 r0, d16[0]
+; CHECK-NEXT: bx lr
%1 = sext <8 x i8> %vec to <8 x i16>
%2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%3 = extractelement <8 x i16> %2, i32 0
@@ -540,7 +779,13 @@ define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
; A constant build_vector created for a vmull with half-width elements must
; not introduce illegal types. <rdar://problem/11324364>
define void @vmull_buildvector() nounwind optsize ssp align 2 {
-; CHECK: vmull_buildvector
+; CHECK-LABEL: vmull_buildvector:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: bxne lr
+; CHECK-NEXT: .LBB55_1: @ %for.body33.lr.ph
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
br i1 undef, label %for.end179, label %for.body.lr.ph
@@ -615,6 +860,9 @@ declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
; creating an illegal type during legalization and causing an assert.
; PR15970
define void @no_illegal_types_vmull_sext(<4 x i32> %a) {
+; CHECK-LABEL: no_illegal_types_vmull_sext:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
%0 = sext <4 x i8> %wide.load283.i to <4 x i32>
@@ -625,6 +873,9 @@ entry:
ret void
}
define void @no_illegal_types_vmull_zext(<4 x i32> %a) {
+; CHECK-LABEL: no_illegal_types_vmull_zext:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
%0 = zext <4 x i8> %wide.load283.i to <4 x i32>
@@ -635,11 +886,16 @@ entry:
ret void
}
-define void @fmul_splat(<4 x float> * %a, <4 x float>* nocapture %dst, float %tmp) nounwind {
+define void @fmul_splat(<4 x float>* %A, <4 x float>* nocapture %dst, float %tmp) nounwind {
; Look for a scalar float rather than a splat, then a vector*scalar multiply.
-; CHECK: vmov s0, r2
-; CHECK: vmul.f32 q8, q8, d0[0]
- %tmp5 = load <4 x float>, <4 x float>* %a, align 4
+; CHECK-LABEL: fmul_splat:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.32 {d16, d17}, [r0]
+; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT: vmul.f32 q8, q8, d0[0]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r1]
+; CHECK-NEXT: bx lr
+ %tmp5 = load <4 x float>, <4 x float>* %A, align 4
%tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
%tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
%tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
@@ -649,14 +905,19 @@ define void @fmul_splat(<4 x float> * %a, <4 x float>* nocapture %dst, float %tm
ret void
}
-define void @fmul_splat_load(<4 x float> * %a, <4 x float>* nocapture %dst, float* nocapture readonly %src) nounwind {
+define void @fmul_splat_load(<4 x float>* %A, <4 x float>* nocapture %dst, float* nocapture readonly %src) nounwind {
; Look for doing a normal scalar FP load rather than an to-all-lanes load,
; then a vector*scalar multiply.
; FIXME: Temporarily broken due to splat representation changes.
-; CHECK: vld1.32 {d18[], d19[]}, [r2:32]
-; CHECK: vmul.f32 q8, q9, q8
+; CHECK-LABEL: fmul_splat_load:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.32 {d16, d17}, [r0]
+; CHECK-NEXT: vld1.32 {d18[], d19[]}, [r2:32]
+; CHECK-NEXT: vmul.f32 q8, q9, q8
+; CHECK-NEXT: vst1.32 {d16, d17}, [r1]
+; CHECK-NEXT: bx lr
%tmp = load float, float* %src, align 4
- %tmp5 = load <4 x float>, <4 x float>* %a, align 4
+ %tmp5 = load <4 x float>, <4 x float>* %A, align 4
%tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
%tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
%tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
diff --git a/llvm/test/CodeGen/ARM/vsub.ll b/llvm/test/CodeGen/ARM/vsub.ll
index 75fb7d493a59..8743fcc47889 100644
--- a/llvm/test/CodeGen/ARM/vsub.ll
+++ b/llvm/test/CodeGen/ARM/vsub.ll
@@ -1,275 +1,370 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubi8:
-;CHECK: vsub.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = sub <8 x i8> %tmp1, %tmp2
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubi16:
-;CHECK: vsub.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = sub <4 x i16> %tmp1, %tmp2
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubi32:
-;CHECK: vsub.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = sub <2 x i32> %tmp1, %tmp2
- ret <2 x i32> %tmp3
-}
-
-define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK-LABEL: vsubi64:
-;CHECK: vsub.i64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
- %tmp3 = sub <1 x i64> %tmp1, %tmp2
- ret <1 x i64> %tmp3
-}
-
-define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vsubf32:
-;CHECK: vsub.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
- %tmp3 = fsub <2 x float> %tmp1, %tmp2
- ret <2 x float> %tmp3
-}
-
-define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubQi8:
-;CHECK: vsub.i8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = sub <16 x i8> %tmp1, %tmp2
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubQi16:
-;CHECK: vsub.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = sub <8 x i16> %tmp1, %tmp2
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubQi32:
-;CHECK: vsub.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = sub <4 x i32> %tmp1, %tmp2
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vsubQi64:
-;CHECK: vsub.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
- %tmp3 = sub <2 x i64> %tmp1, %tmp2
- ret <2 x i64> %tmp3
-}
-
-define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vsubQf32:
-;CHECK: vsub.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
- %tmp3 = fsub <4 x float> %tmp1, %tmp2
- ret <4 x float> %tmp3
-}
-
-define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind {
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vsubi8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i8 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <8 x i8> %A, %B
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsubi16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i16 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <4 x i16> %A, %B
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsubi32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i32 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <2 x i32> %A, %B
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vsubi64(<1 x i64> %A, <1 x i64> %B) {
+; CHECK-LABEL: vsubi64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i64 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <1 x i64> %A, %B
+ ret <1 x i64> %tmp3
+}
+
+define <2 x float> @vsubf32(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: vsubf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.f32 d0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = fsub <2 x float> %A, %B
+ ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vsubQi8(<16 x i8> %A, <16 x i8> %B) {
+; CHECK-LABEL: vsubQi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i8 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <16 x i8> %A, %B
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vsubQi16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vsubQi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i16 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <8 x i16> %A, %B
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsubQi32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vsubQi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i32 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <4 x i32> %A, %B
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsubQi64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vsubQi64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.i64 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = sub <2 x i64> %A, %B
+ ret <2 x i64> %tmp3
+}
+
+define <4 x float> @vsubQf32(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: vsubQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsub.f32 q0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = fsub <4 x float> %A, %B
+ ret <4 x float> %tmp3
+}
+
+define <8 x i8> @vrsubhni16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vrsubhni16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vrsubhn.i16 d0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %A, <8 x i16> %B)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vrsubhni32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vrsubhni32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vrsubhn.i32 d0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %A, <4 x i32> %B)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vrsubhni64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vrsubhni64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vrsubhn.i64 d0, q0, q1
+; CHECK-NEXT: bx lr
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %A, <2 x i64> %B)
+ ret <2 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) readnone
+declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) readnone
+declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) readnone
+
+define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) {
; CHECK-LABEL: vsubhni16_natural:
-; CHECK: vsubhn.i16
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubhn.i16 d0, q0, q1
+; CHECK-NEXT: bx lr
%sum = sub <8 x i16> %A, %B
%shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%trunc = trunc <8 x i16> %shift to <8 x i8>
ret <8 x i8> %trunc
}
-define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind {
+define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) {
; CHECK-LABEL: vsubhni32_natural:
-; CHECK: vsubhn.i32
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubhn.i32 d0, q0, q1
+; CHECK-NEXT: bx lr
%sum = sub <4 x i32> %A, %B
%shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
%trunc = trunc <4 x i32> %shift to <4 x i16>
ret <4 x i16> %trunc
}
-define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind {
+define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) {
; CHECK-LABEL: vsubhni64_natural:
-; CHECK: vsubhn.i64
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubhn.i64 d0, q0, q1
+; CHECK-NEXT: bx lr
%sum = sub <2 x i64> %A, %B
%shift = lshr <2 x i64> %sum, <i64 32, i64 32>
%trunc = trunc <2 x i64> %shift to <2 x i32>
ret <2 x i32> %trunc
}
-define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vrsubhni16:
-;CHECK: vrsubhn.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vrsubhni32:
-;CHECK: vrsubhn.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vrsubhni64:
-;CHECK: vrsubhn.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
- %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubls8:
-;CHECK: vsubl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = sub <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubls16:
-;CHECK: vsubl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = sub <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubls32:
-;CHECK: vsubl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = sub <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsublu8:
-;CHECK: vsubl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = sub <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsublu16:
-;CHECK: vsubl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = sub <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsublu32:
-;CHECK: vsubl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = sub <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubws8:
-;CHECK: vsubw.s8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = sub <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubws16:
-;CHECK: vsubw.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = sub <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubws32:
-;CHECK: vsubw.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = sub <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubwu8:
-;CHECK: vsubw.u8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = sub <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubwu16:
-;CHECK: vsubw.u16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = sub <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubwu32:
-;CHECK: vsubw.u32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = sub <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
+define <8 x i16> @vsubls8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubls8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubl.s8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <8 x i8> %A to <8 x i16>
+ %tmp4 = sext <8 x i8> %B to <8 x i16>
+ %tmp5 = sub <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vsubls16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubls16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubl.s16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <4 x i16> %A to <4 x i32>
+ %tmp4 = sext <4 x i16> %B to <4 x i32>
+ %tmp5 = sub <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vsubls32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubls32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubl.s32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <2 x i32> %A to <2 x i64>
+ %tmp4 = sext <2 x i32> %B to <2 x i64>
+ %tmp5 = sub <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vsublu8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsublu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubl.u8 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %A to <8 x i16>
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = sub <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vsublu16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsublu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubl.u16 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %A to <4 x i32>
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = sub <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vsublu32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsublu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubl.u32 q0, d0, d1
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %A to <2 x i64>
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = sub <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vsubla8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubla8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d1
+; CHECK-NEXT: vmovl.u8 q9, d0
+; CHECK-NEXT: vsub.i16 q0, q9, q8
+; CHECK-NEXT: vbic.i16 q0, #0xff00
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %A to <8 x i16>
+ %tmp4 = zext <8 x i8> %B to <8 x i16>
+ %tmp5 = sub <8 x i16> %tmp3, %tmp4
+ %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ ret <8 x i16> %and
+}
+
+define <4 x i32> @vsubla16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubla16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u16 q8, d1
+; CHECK-NEXT: vmovl.u16 q9, d0
+; CHECK-NEXT: vmov.i32 q10, #0xffff
+; CHECK-NEXT: vsub.i32 q8, q9, q8
+; CHECK-NEXT: vand q0, q8, q10
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %A to <4 x i32>
+ %tmp4 = zext <4 x i16> %B to <4 x i32>
+ %tmp5 = sub <4 x i32> %tmp3, %tmp4
+ %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define <2 x i64> @vsubla32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubla32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u32 q8, d1
+; CHECK-NEXT: vmovl.u32 q9, d0
+; CHECK-NEXT: vmov.i64 q10, #0xffffffff
+; CHECK-NEXT: vsub.i64 q8, q9, q8
+; CHECK-NEXT: vand q0, q8, q10
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %A to <2 x i64>
+ %tmp4 = zext <2 x i32> %B to <2 x i64>
+ %tmp5 = sub <2 x i64> %tmp3, %tmp4
+ %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
+}
+
+define <8 x i16> @vsubws8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubws8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubw.s8 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <8 x i8> %B to <8 x i16>
+ %tmp4 = sub <8 x i16> %A, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsubws16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubws16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubw.s16 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <4 x i16> %B to <4 x i32>
+ %tmp4 = sub <4 x i32> %A, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsubws32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubws32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubw.s32 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = sext <2 x i32> %B to <2 x i64>
+ %tmp4 = sub <2 x i64> %A, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vsubwu8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubwu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubw.u8 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %B to <8 x i16>
+ %tmp4 = sub <8 x i16> %A, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsubwu16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubwu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubw.u16 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %B to <4 x i32>
+ %tmp4 = sub <4 x i32> %A, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsubwu32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubwu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vsubw.u32 q0, q0, d2
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %B to <2 x i64>
+ %tmp4 = sub <2 x i64> %A, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vsubwa8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubwa8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u8 q8, d2
+; CHECK-NEXT: vsub.i16 q0, q0, q8
+; CHECK-NEXT: vbic.i16 q0, #0xff00
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <8 x i8> %B to <8 x i16>
+ %tmp4 = sub <8 x i16> %A, %tmp3
+ %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+ ret <8 x i16> %and
+}
+
+define <4 x i32> @vsubwa16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubwa16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u16 q8, d2
+; CHECK-NEXT: vmov.i32 q9, #0xffff
+; CHECK-NEXT: vsub.i32 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <4 x i16> %B to <4 x i32>
+ %tmp4 = sub <4 x i32> %A, %tmp3
+ %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
+ ret <4 x i32> %and
+}
+
+define <2 x i64> @vsubwa32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubwa32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovl.u32 q8, d2
+; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: vsub.i64 q8, q0, q8
+; CHECK-NEXT: vand q0, q8, q9
+; CHECK-NEXT: bx lr
+ %tmp3 = zext <2 x i32> %B to <2 x i64>
+ %tmp4 = sub <2 x i64> %A, %tmp3
+ %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
+ ret <2 x i64> %and
}
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