[llvm-branch-commits] [llvm] 413596e - [RISCV] Teach debug output from assembly parser to print register names instead of enum values.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-12-14T17:22:55-08:00
New Revision: 413596ee45d327a7254d9f3d5f89bf58bbcbb310

URL: https://github.com/llvm/llvm-project/commit/413596ee45d327a7254d9f3d5f89bf58bbcbb310
DIFF: https://github.com/llvm/llvm-project/commit/413596ee45d327a7254d9f3d5f89bf58bbcbb310.diff

LOG: [RISCV] Teach debug output from assembly parser to print register names instead of enum values.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index cfbf3c51736c..4bb971368e83 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -7,6 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/RISCVAsmBackend.h"
+#include "MCTargetDesc/RISCVInstPrinter.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "MCTargetDesc/RISCVTargetStreamer.h"
@@ -737,13 +738,19 @@ struct RISCVOperand : public MCParsedAsmOperand {
   }
 
   void print(raw_ostream &OS) const override {
+    auto RegName = [](unsigned Reg) {
+      if (Reg)
+        return RISCVInstPrinter::getRegisterName(Reg);
+      else
+        return "noreg";
+    };
+
     switch (Kind) {
     case KindTy::Immediate:
       OS << *getImm();
       break;
     case KindTy::Register:
-      OS << "<register x";
-      OS << getReg() << ">";
+      OS << "<register " << RegName(getReg()) << ">";
       break;
     case KindTy::Token:
       OS << "'" << getToken() << "'";