[llvm-branch-commits] [llvm-branch] r368423 - Merging r368324:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Fri Aug  9 02:56:27 2019
New Revision: 368423

URL: http://llvm.org/viewvc/llvm-project?rev=368423&view=rev
Log:
Merging r368324:
------------------------------------------------------------------------
r368324 | ctopper | 2019-08-08 20:11:17 +0200 (Thu, 08 Aug 2019) | 7 lines

[X86] Make CMPXCHG16B feature imply CMPXCHG8B feature.

This fixes znver1 so that it properly enables CMPXHG8B. We can
probably remove explicit CMPXCHG8B from CPUs that also have
CMPXCHG16B, but keeping this simple to allow cherry pick to 9.0.

Fixes PR42935.
------------------------------------------------------------------------

Modified:
    llvm/branches/release_90/   (props changed)
    llvm/branches/release_90/lib/Target/X86/X86.td
    llvm/branches/release_90/test/CodeGen/X86/cmpxchg8b.ll

Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug  9 02:56:27 2019
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367417,367662,367750,367753,367846-367847,367898,367941,368004,368315
+/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367417,367662,367750,367753,367846-367847,367898,367941,368004,368315,368324

Modified: llvm/branches/release_90/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/X86/X86.td?rev=368423&r1=368422&r2=368423&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/X86/X86.td (original)
+++ llvm/branches/release_90/lib/Target/X86/X86.td Fri Aug  9 02:56:27 2019
@@ -95,7 +95,8 @@ def Feature3DNowA  : SubtargetFeature<"3
 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
                                       "Support 64-bit instructions">;
 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
-                                      "64-bit with cmpxchg16b">;
+                                      "64-bit with cmpxchg16b",
+                                      [FeatureCMPXCHG8B]>;
 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
                                        "SHLD instruction is slow">;
 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",

Modified: llvm/branches/release_90/test/CodeGen/X86/cmpxchg8b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/X86/cmpxchg8b.ll?rev=368423&r1=368422&r2=368423&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/X86/cmpxchg8b.ll (original)
+++ llvm/branches/release_90/test/CodeGen/X86/cmpxchg8b.ll Fri Aug  9 02:56:27 2019
@@ -2,6 +2,7 @@
 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86
 ; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64
 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=i486 | FileCheck %s --check-prefixes=I486
+; RUN: llc < %s -mtriple=i686-unknown- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,X86
 
 ; Basic 64-bit cmpxchg
 define void @t1(i64* nocapture %p) nounwind ssp {