[llvm-branch-commits] [llvm-branch] r367991 - Merging r366660 and r367306:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Aug 6 01:08:11 PDT 2019
Author: hans
Date: Tue Aug 6 01:08:11 2019
New Revision: 367991
URL: http://llvm.org/viewvc/llvm-project?rev=367991&view=rev
Log:
Merging r366660 and r367306:
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r366660 | rksimon | 2019-07-21 21:04:44 +0200 (Sun, 21 Jul 2019) | 3 lines
[X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_BROADCAST narrowing handling. NFCI.
Move the narrowing of SUBV_BROADCAST to where we handle all the other opcodes.
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r367306 | rksimon | 2019-07-30 13:35:13 +0200 (Tue, 30 Jul 2019) | 5 lines
[X86][AVX] SimplifyDemandedVectorElts - handle extraction from X86ISD::SUBV_BROADCAST source (PR42819)
PR42819 showed an issue that we couldn't handle the case where we demanded a 'sub-sub-vector' of the SUBV_BROADCAST 'sub-vector' source.
This patch recognizes these cases and extracts the sub-sub-vector instead of trying to broadcast to a type smaller than the 'sub-vector' source.
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Modified:
llvm/branches/release_90/ (props changed)
llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_90/test/CodeGen/X86/oddsubvector.ll
Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 6 01:08:11 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366481,366487,366527,366570,366868,366925,367030,367062,367124,367215,367292,367304,367314,367340-367341,367394,367396,367398,367417,367662,367753,367846-367847
+/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367417,367662,367753,367846-367847
Modified: llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp?rev=367991&r1=367990&r2=367991&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp Tue Aug 6 01:08:11 2019
@@ -34062,25 +34062,6 @@ bool X86TargetLowering::SimplifyDemanded
return true;
break;
}
- case X86ISD::SUBV_BROADCAST: {
- // Reduce size of broadcast if we don't need the upper half.
- unsigned HalfElts = NumElts / 2;
- if (DemandedElts.extractBits(HalfElts, HalfElts).isNullValue()) {
- SDValue Src = Op.getOperand(0);
- MVT SrcVT = Src.getSimpleValueType();
-
- SDValue Half = Src;
- if (SrcVT.getVectorNumElements() != HalfElts) {
- MVT HalfVT = MVT::getVectorVT(SrcVT.getScalarType(), HalfElts);
- Half = TLO.DAG.getNode(X86ISD::SUBV_BROADCAST, SDLoc(Op), HalfVT, Src);
- }
-
- return TLO.CombineTo(Op, insertSubVector(TLO.DAG.getUNDEF(VT), Half, 0,
- TLO.DAG, SDLoc(Op),
- Half.getValueSizeInBits()));
- }
- break;
- }
case X86ISD::VPERMV: {
SDValue Mask = Op.getOperand(0);
APInt MaskUndef, MaskZero;
@@ -34135,6 +34116,21 @@ bool X86TargetLowering::SimplifyDemanded
insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits);
return TLO.CombineTo(Op, Insert);
}
+ // Subvector broadcast.
+ case X86ISD::SUBV_BROADCAST: {
+ SDLoc DL(Op);
+ SDValue Src = Op.getOperand(0);
+ if (Src.getValueSizeInBits() > ExtSizeInBits)
+ Src = extractSubVector(Src, 0, TLO.DAG, DL, ExtSizeInBits);
+ else if (Src.getValueSizeInBits() < ExtSizeInBits) {
+ MVT SrcSVT = Src.getSimpleValueType().getScalarType();
+ MVT SrcVT =
+ MVT::getVectorVT(SrcSVT, ExtSizeInBits / SrcSVT.getSizeInBits());
+ Src = TLO.DAG.getNode(X86ISD::SUBV_BROADCAST, DL, SrcVT, Src);
+ }
+ return TLO.CombineTo(Op, insertSubVector(TLO.DAG.getUNDEF(VT), Src, 0,
+ TLO.DAG, DL, ExtSizeInBits));
+ }
// Byte shifts by immediate.
case X86ISD::VSHLDQ:
case X86ISD::VSRLDQ:
Modified: llvm/branches/release_90/test/CodeGen/X86/oddsubvector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/X86/oddsubvector.ll?rev=367991&r1=367990&r2=367991&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/X86/oddsubvector.ll (original)
+++ llvm/branches/release_90/test/CodeGen/X86/oddsubvector.ll Tue Aug 6 01:08:11 2019
@@ -158,3 +158,35 @@ define void @PR40815(%struct.Mat4* nocap
store <4 x float> %5, <4 x float>* %13, align 16
ret void
}
+
+define <16 x i32> @PR42819(<8 x i32>* %a0) {
+; SSE-LABEL: PR42819:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqu (%rdi), %xmm3
+; SSE-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7,8,9,10,11]
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: xorps %xmm2, %xmm2
+; SSE-NEXT: retq
+;
+; AVX-LABEL: PR42819:
+; AVX: # %bb.0:
+; AVX-NEXT: vpermilps {{.*#+}} xmm0 = mem[0,0,1,2]
+; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm0[5,6,7]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: PR42819:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovdqu (%rdi), %xmm0
+; AVX512-NEXT: movw $-8192, %ax # imm = 0xE000
+; AVX512-NEXT: kmovw %eax, %k1
+; AVX512-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z}
+; AVX512-NEXT: retq
+ %1 = load <8 x i32>, <8 x i32>* %a0, align 4
+ %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %3 = shufflevector <16 x i32> zeroinitializer, <16 x i32> %2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
+ ret <16 x i32> %3
+}
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