[llvm-branch-commits] [llvm-branch] r367810 - Merging r366868:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Mon Aug  5 01:10:53 2019
New Revision: 367810

URL: http://llvm.org/viewvc/llvm-project?rev=367810&view=rev
Log:
Merging r366868:
------------------------------------------------------------------------
r366868 | rogfer01 | 2019-07-24 07:33:46 +0200 (Wed, 24 Jul 2019) | 6 lines

[RISCV] Implement benchmark::cycleclock::Now

This is a cherrypick of D64237 onto llvm/utils/benchmark and
libcxx/utils/google-benchmark.

Differential Revision: https://reviews.llvm.org/D65142
------------------------------------------------------------------------

Modified:
    llvm/branches/release_90/   (props changed)
    llvm/branches/release_90/utils/benchmark/README.LLVM
    llvm/branches/release_90/utils/benchmark/src/cycleclock.h

Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Aug  5 01:10:53 2019
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366481,366487,366527,366570,366925,367030,367062,367124,367215,367292,367304,367314,367340-367341,367394,367396,367398,367417,367753
+/llvm/trunk:155241,366431,366481,366487,366527,366570,366868,366925,367030,367062,367124,367215,367292,367304,367314,367340-367341,367394,367396,367398,367417,367753

Modified: llvm/branches/release_90/utils/benchmark/README.LLVM
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/utils/benchmark/README.LLVM?rev=367810&r1=367809&r2=367810&view=diff
==============================================================================
--- llvm/branches/release_90/utils/benchmark/README.LLVM (original)
+++ llvm/branches/release_90/utils/benchmark/README.LLVM Mon Aug  5 01:10:53 2019
@@ -23,3 +23,5 @@ Changes:
   is applied to disable exceptions in Microsoft STL when exceptions are disabled
 * Disabled CMake get_git_version as it is meaningless for this in-tree build,
   and hardcoded a null version
+* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
+  is applied on top of v1.4.1 to add RISC-V timer support.

Modified: llvm/branches/release_90/utils/benchmark/src/cycleclock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/utils/benchmark/src/cycleclock.h?rev=367810&r1=367809&r2=367810&view=diff
==============================================================================
--- llvm/branches/release_90/utils/benchmark/src/cycleclock.h (original)
+++ llvm/branches/release_90/utils/benchmark/src/cycleclock.h Mon Aug  5 01:10:53 2019
@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t N
   uint64_t tsc;
   asm("stck %0" : "=Q" (tsc) : : "cc");
   return tsc;
+#elif defined(__riscv) // RISC-V
+  // Use RDCYCLE (and RDCYCLEH on riscv32)
+#if __riscv_xlen == 32
+  uint64_t cycles_low, cycles_hi0, cycles_hi1;
+  asm("rdcycleh %0" : "=r"(cycles_hi0));
+  asm("rdcycle %0" : "=r"(cycles_lo));
+  asm("rdcycleh %0" : "=r"(cycles_hi1));
+  // This matches the PowerPC overflow detection, above
+  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
+  return (cycles_hi1 << 32) | cycles_lo;
+#else
+  uint64_t cycles;
+  asm("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#endif
 #else
 // The soft failover to a generic implementation is automatic only for ARM.
 // For other platforms the developer is expected to make an attempt to create