[llvm-branch-commits] [llvm-branch] r293651 - Merging r293417:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Jan 31 09:23:10 PST 2017
Author: hans
Date: Tue Jan 31 11:23:10 2017
New Revision: 293651
URL: http://llvm.org/viewvc/llvm-project?rev=293651&view=rev
Log:
Merging r293417:
------------------------------------------------------------------------
r293417 | jhibbits | 2017-01-28 20:55:57 -0800 (Sat, 28 Jan 2017) | 16 lines
Add some Book-E instructions to the asm parser and printer.
Summary:
Adds the following instructions:
* mfpmr
* mtpmr
* icblc
* icblq
* icbtls
Fix the scheduling for mtspr on e5500, which uses CFX0, instead of
SFX0/SFX1 as on e500mc.
Addresses PR 31538.
Differential Revision: https://reviews.llvm.org/D29002
------------------------------------------------------------------------
Modified:
llvm/branches/release_40/ (props changed)
llvm/branches/release_40/lib/Target/PowerPC/PPCInstrInfo.td
llvm/branches/release_40/lib/Target/PowerPC/PPCSchedule.td
llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE500mc.td
llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE5500.td
llvm/branches/release_40/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
llvm/branches/release_40/test/MC/PowerPC/ppc64-encoding-bookIII.s
Propchange: llvm/branches/release_40/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Jan 31 11:23:10 2017
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,291858-291859,291863,291875,291909,291918,291966,291968,291979,292133,292242,292254-292255,292280,292323,292444,292467,292516,292583,292625,292641,292651,292667,292711-292713,292758,293021,293025,293259,293291,293293,293522
+/llvm/trunk:155241,291858-291859,291863,291875,291909,291918,291966,291968,291979,292133,292242,292254-292255,292280,292323,292444,292467,292516,292583,292625,292641,292651,292667,292711-292713,292758,293021,293025,293259,293291,293293,293417,293522
Modified: llvm/branches/release_40/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/PowerPC/PPCInstrInfo.td?rev=293651&r1=293650&r2=293651&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/branches/release_40/lib/Target/PowerPC/PPCInstrInfo.td Tue Jan 31 11:23:10 2017
@@ -1508,8 +1508,14 @@ def DCBTST : DCB_Form_hint<246, (outs),
PPC970_DGroup_Single;
} // hasSideEffects = 0
+def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src),
+ "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>;
+def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src),
+ "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
"icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
+def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
+ "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
def : Pat<(int_ppc_dcbt xoaddr:$dst),
(DCBT 0, xoaddr:$dst)>;
@@ -2381,6 +2387,13 @@ def MTSPR : XFXForm_1<31, 467, (outs), (
def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
"mftb $RT, $SPR", IIC_SprMFTB>;
+def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
+ "mfpmr $RT, $SPR", IIC_SprMFPMR>;
+
+def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
+ "mtpmr $SPR, $RT", IIC_SprMTPMR>;
+
+
// A pseudo-instruction used to implement the read of the 64-bit cycle counter
// on a 32-bit target.
let hasSideEffects = 1, usesCustomInserter = 1 in
Modified: llvm/branches/release_40/lib/Target/PowerPC/PPCSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/PowerPC/PPCSchedule.td?rev=293651&r1=293650&r2=293651&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/PowerPC/PPCSchedule.td (original)
+++ llvm/branches/release_40/lib/Target/PowerPC/PPCSchedule.td Tue Jan 31 11:23:10 2017
@@ -118,6 +118,8 @@ def IIC_SprTLBIE : InstrItinClass;
def IIC_SprABORT : InstrItinClass;
def IIC_SprMSGSYNC : InstrItinClass;
def IIC_SprSTOP : InstrItinClass;
+def IIC_SprMFPMR : InstrItinClass;
+def IIC_SprMTPMR : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
Modified: llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE500mc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE500mc.td?rev=293651&r1=293650&r2=293651&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE500mc.td (original)
+++ llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE500mc.td Tue Jan 31 11:23:10 2017
@@ -249,6 +249,10 @@ def PPCE500mcItineraries : ProcessorItin
InstrStage<5, [E500_SFX0]>],
[8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>,
+ InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<4, [E500_SFX0]>],
+ [7, 1], // Latency = 4, Repeat rate = 4
+ [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
@@ -257,6 +261,10 @@ def PPCE500mcItineraries : ProcessorItin
InstrStage<1, [E500_SFX0, E500_SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_GPR_Bypass, E500_CR_Bypass]>,
+ InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<1, [E500_SFX0]>],
+ [4, 1], // Latency = 1, Repeat rate = 1
+ [E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
Modified: llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE5500.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE5500.td?rev=293651&r1=293650&r2=293651&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE5500.td (original)
+++ llvm/branches/release_40/lib/Target/PowerPC/PPCScheduleE5500.td Tue Jan 31 11:23:10 2017
@@ -313,20 +313,24 @@ def PPCE5500Itineraries : ProcessorItine
InstrStage<5, [E5500_CFX_0]>],
[9, 2], // Latency = 5, Repeat rate = 5
[E5500_GPR_Bypass, E5500_CR_Bypass]>,
- InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
- InstrStage<4, [E5500_SFX0]>],
+ InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<4, [E5500_CFX_0]>],
[8, 2], // Latency = 4, Repeat rate = 4
[E5500_GPR_Bypass, E5500_GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_CFX_0]>],
[5], // Latency = 1, Repeat rate = 1
[E5500_GPR_Bypass]>,
+ InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<1, [E5500_CFX_0]>],
+ [5], // Latency = 1, Repeat rate = 1
+ [E5500_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<4, [E5500_CFX_0]>],
[8, 2], // Latency = 4, Repeat rate = 4
[NoBypass, E5500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
- InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
+ InstrStage<1, [E5500_CFX_0]>],
[5], // Latency = 1, Repeat rate = 1
[E5500_GPR_Bypass]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
Modified: llvm/branches/release_40/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt?rev=293651&r1=293650&r2=293651&view=diff
==============================================================================
--- llvm/branches/release_40/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt (original)
+++ llvm/branches/release_40/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt Tue Jan 31 11:23:10 2017
@@ -134,3 +134,12 @@
0x7c 0x0b 0x66 0x24
# CHECK: tlbsx 11, 12
0x7c 0x0b 0x67 0x24
+
+# CHECK: mfpmr 5, 400
+0x7c 0xb0 0x62 0x9c
+# CHECK: mtpmr 400, 6
+0x7c 0xd0 0x63 0x9c
+# CHECK: icblc 0, 0, 8
+0x7c 0x00 0x41 0xcc
+# CHECK: icbtls 0, 0, 9
+0x7c 0x00 0x4b 0xcc
Modified: llvm/branches/release_40/test/MC/PowerPC/ppc64-encoding-bookIII.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/MC/PowerPC/ppc64-encoding-bookIII.s?rev=293651&r1=293650&r2=293651&view=diff
==============================================================================
--- llvm/branches/release_40/test/MC/PowerPC/ppc64-encoding-bookIII.s (original)
+++ llvm/branches/release_40/test/MC/PowerPC/ppc64-encoding-bookIII.s Tue Jan 31 11:23:10 2017
@@ -197,3 +197,16 @@
# CHECK-BE: tlbsx 11, 12 # encoding: [0x7c,0x0b,0x67,0x24]
# CHECK-LE: tlbsx 11, 12 # encoding: [0x24,0x67,0x0b,0x7c]
tlbsx %r11, %r12
+
+# CHECK-BE: mfpmr 5, 400 # encoding: [0x7c,0xb0,0x62,0x9c]
+# CHECK-LE: mfpmr 5, 400 # encoding: [0x9c,0x62,0xb0,0x7c]
+ mfpmr 5, 400
+# CHECK-BE: mtpmr 400, 6 # encoding: [0x7c,0xd0,0x63,0x9c]
+# CHECK-LE: mtpmr 400, 6 # encoding: [0x9c,0x63,0xd0,0x7c]
+ mtpmr 400, 6
+# CHECK-BE: icblc 0, 0, 8 # encoding: [0x7c,0x00,0x41,0xcc]
+# CHECK-LE: icblc 0, 0, 8 # encoding: [0xcc,0x41,0x00,0x7c]
+ icblc 0, 0, 8
+# CHECK-BE: icbtls 0, 0, 9 # encoding: [0x7c,0x00,0x4b,0xcc]
+# CHECK-LE: icbtls 0, 0, 9 # encoding: [0xcc,0x4b,0x00,0x7c]
+ icbtls 0, 0, 9
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