[llvm-branch-commits] [llvm-branch] r245578 - Merge r245577 into branch_37

[Renato Golin via llvm-branch-commits]

Author: rengolin
Date: Thu Aug 20 11:41:22 2015
New Revision: 245578

URL: http://llvm.org/viewvc/llvm-project?rev=245578&view=rev
Log:
Merge r245577 into branch_37

[ARM] Don't try and custom lower a vNi64 SETCC.

It won't go well. We've already marked 64-bit SETCCs as non-Custom, but it's
just possible that a SETCC has a legal result type but an illegal operand
type. If this happens, bail out before we create unselectable nodes.

Fixes PR24292. I tried to create a testcase but in 99% of cases we can't
trigger this - not surprising that this bug has been latent since 2009.

Modified:
    llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp?rev=245578&r1=245577&r2=245578&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 20 11:41:22 2015
@@ -4583,6 +4583,12 @@ static SDValue LowerVSETCC(SDValue Op, S
   ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
   SDLoc dl(Op);
 
+  if (CmpVT.getVectorElementType() == MVT::i64)
+    // 64-bit comparisons are not legal. We've marked SETCC as non-Custom,
+    // but it's possible that our operands are 64-bit but our result is 32-bit.
+    // Bail in this case.
+    return SDValue();
+
   if (Op1.getValueType().isFloatingPoint()) {
     switch (SetCCOpcode) {
     default: llvm_unreachable("Illegal FP comparison");