[llvm-branch-commits] [llvm-branch] r236020 - Merging r229752:

[Tom Stellard]

Author: tstellar
Date: Tue Apr 28 14:12:16 2015
New Revision: 236020

URL: http://llvm.org/viewvc/llvm-project?rev=236020&view=rev
Log:
Merging r229752:

------------------------------------------------------------------------
r229752 | marek.olsak | 2015-02-18 17:12:45 -0500 (Wed, 18 Feb 2015) | 10 lines

R600/SI: Fix READLANE and WRITELANE lane select for VI

VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.

This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td
    llvm/branches/release_36/lib/Target/R600/SIInstructions.td

Modified: llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td?rev=236020&r1=236019&r2=236020&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td Tue Apr 28 14:12:16 2015
@@ -297,14 +297,13 @@ class VOP1e <bits<8> op> : Enc32 {
 }
 
 class VOP2e <bits<6> op> : Enc32 {
+  bits<8> vdst;
+  bits<9> src0;
+  bits<8> src1;
 
-  bits<8> VDST;
-  bits<9> SRC0;
-  bits<8> VSRC1;
-
-  let Inst{8-0} = SRC0;
-  let Inst{16-9} = VSRC1;
-  let Inst{24-17} = VDST;
+  let Inst{8-0} = src0;
+  let Inst{16-9} = src1;
+  let Inst{24-17} = vdst;
   let Inst{30-25} = op;
   let Inst{31} = 0x0; //encoding
 }

Modified: llvm/branches/release_36/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstructions.td?rev=236020&r1=236019&r2=236020&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstructions.td (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstructions.td Tue Apr 28 14:12:16 2015
@@ -1508,16 +1508,16 @@ defm V_READLANE_B32 : VOP2SI_3VI_m <
   vop3 <0x001, 0x289>,
   "v_readlane_b32",
   (outs SReg_32:$vdst),
-  (ins VGPR_32:$src0, SSrc_32:$vsrc1),
-  "v_readlane_b32 $vdst, $src0, $vsrc1"
+  (ins VGPR_32:$src0, SCSrc_32:$src1),
+  "v_readlane_b32 $vdst, $src0, $src1"
 >;
 
 defm V_WRITELANE_B32 : VOP2SI_3VI_m <
   vop3 <0x002, 0x28a>,
   "v_writelane_b32",
   (outs VGPR_32:$vdst),
-  (ins SReg_32:$src0, SSrc_32:$vsrc1),
-  "v_writelane_b32 $vdst, $src0, $vsrc1"
+  (ins SReg_32:$src0, SCSrc_32:$src1),
+  "v_writelane_b32 $vdst, $src0, $src1"
 >;
 
 // These instructions only exist on SI and CI