[llvm-branch-commits] [llvm-branch] r236019 - Merging r229751:
Tom Stellard
thomas.stellard at amd.com
Tue Apr 28 12:12:14 PDT 2015
Author: tstellar
Date: Tue Apr 28 14:12:14 2015
New Revision: 236019
URL: http://llvm.org/viewvc/llvm-project?rev=236019&view=rev
Log:
Merging r229751:
------------------------------------------------------------------------
r229751 | marek.olsak | 2015-02-18 17:12:41 -0500 (Wed, 18 Feb 2015) | 2 lines
R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_C
------------------------------------------------------------------------
Modified:
llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp
Modified: llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp?rev=236019&r1=236018&r2=236019&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp Tue Apr 28 14:12:14 2015
@@ -1140,6 +1140,8 @@ bool SIInstrInfo::verifyInstruction(cons
return false;
}
+ int RegClass = Desc.OpInfo[i].RegClass;
+
switch (Desc.OpInfo[i].OperandType) {
case MCOI::OPERAND_REGISTER:
if (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm()) {
@@ -1150,7 +1152,7 @@ bool SIInstrInfo::verifyInstruction(cons
case AMDGPU::OPERAND_REG_IMM32:
break;
case AMDGPU::OPERAND_REG_INLINE_C:
- if (MI->getOperand(i).isImm() && !isInlineConstant(MI->getOperand(i))) {
+ if (isLiteralConstant(MI->getOperand(i))) {
ErrInfo = "Illegal immediate value for operand.";
return false;
}
@@ -1171,7 +1173,6 @@ bool SIInstrInfo::verifyInstruction(cons
if (!MI->getOperand(i).isReg())
continue;
- int RegClass = Desc.OpInfo[i].RegClass;
if (RegClass != -1) {
unsigned Reg = MI->getOperand(i).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
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