[llvm-branch-commits] [llvm-branch] r236021 - Merging r230146:

[Tom Stellard]

Author: tstellar
Date: Tue Apr 28 14:12:19 2015
New Revision: 236021

URL: http://llvm.org/viewvc/llvm-project?rev=236021&view=rev
Log:
Merging r230146:

------------------------------------------------------------------------
r230146 | Matthew.Arsenault | 2015-02-21 16:29:00 -0500 (Sat, 21 Feb 2015) | 2 lines

R600/SI: Fix mad*k definitions

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
    llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td
    llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td
    llvm/branches/release_36/lib/Target/R600/SIInstructions.td

Modified: llvm/branches/release_36/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp?rev=236021&r1=236020&r2=236021&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp Tue Apr 28 14:12:19 2015
@@ -291,6 +291,8 @@ void AMDGPUInstPrinter::printOperand(con
         printImmediate64(Op.getImm(), O);
       else
         llvm_unreachable("Invalid register class size");
+    } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
+      printImmediate32(Op.getImm(), O);
     } else {
       // We hit this for the immediate instruction bits that don't yet have a
       // custom printer.

Modified: llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td?rev=236021&r1=236020&r2=236021&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstrFormats.td Tue Apr 28 14:12:19 2015
@@ -308,6 +308,21 @@ class VOP2e <bits<6> op> : Enc32 {
   let Inst{31} = 0x0; //encoding
 }
 
+class VOP2_MADKe <bits<6> op> : Enc64 {
+
+  bits<8>  vdst;
+  bits<9>  src0;
+  bits<8>  vsrc1;
+  bits<32> src2;
+
+  let Inst{8-0} = src0;
+  let Inst{16-9} = vsrc1;
+  let Inst{24-17} = vdst;
+  let Inst{30-25} = op;
+  let Inst{31} = 0x0; // encoding
+  let Inst{63-32} = src2;
+}
+
 class VOP3e <bits<9> op> : Enc64 {
 
   bits<8> dst;

Modified: llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td?rev=236021&r1=236020&r2=236021&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td Tue Apr 28 14:12:19 2015
@@ -807,6 +807,10 @@ def VOP_I64_I32_I64 : VOPProfile <[i64,
 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
 
 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
+def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
+  field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
+  field string Asm = " $dst, $src0, $vsrc1, $src2";
+}
 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
@@ -1192,6 +1196,23 @@ multiclass VOP2_VI3_Inst <vop23 op, stri
   revOp, P.HasModifiers
 >;
 
+multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
+
+  def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
+
+let isCodeGenOnly = 0 in {
+  def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
+                        !strconcat(opName, VOP_MADK.Asm), []>,
+            SIMCInstr <opName#"_e32", SISubtarget.SI>,
+            VOP2_MADKe <op.SI>;
+
+  def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
+                        !strconcat(opName, VOP_MADK.Asm), []>,
+            SIMCInstr <opName#"_e32", SISubtarget.VI>,
+            VOP2_MADKe <op.VI>;
+} // End isCodeGenOnly = 0
+}
+
 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
   VOPCCommon <ins, "", pattern>,
   VOP <opName>,

Modified: llvm/branches/release_36/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstructions.td?rev=236021&r1=236020&r2=236021&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstructions.td (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstructions.td Tue Apr 28 14:12:19 2015
@@ -1469,10 +1469,10 @@ defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x
 defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_F32_F32_F32>;
 } // End isCommutable = 1
 
-defm V_MADMK_F32 : VOP2Inst <vop2<0x20, 0x17>, "v_madmk_f32", VOP_F32_F32_F32>;
+defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32">;
 
 let isCommutable = 1 in {
-defm V_MADAK_F32 : VOP2Inst <vop2<0x21, 0x18>, "v_madak_f32", VOP_F32_F32_F32>;
+defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32">;
 } // End isCommutable = 1
 
 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC