[llvm-branch-commits] [llvm-branch] r236022 - Merging r230147:

Tom Stellard thomas.stellard at amd.com
Tue Apr 28 12:12:21 PDT 2015


Author: tstellar
Date: Tue Apr 28 14:12:20 2015
New Revision: 236022

URL: http://llvm.org/viewvc/llvm-project?rev=236022&view=rev
Log:
Merging r230147:

------------------------------------------------------------------------
r230147 | Matthew.Arsenault | 2015-02-21 16:29:04 -0500 (Sat, 21 Feb 2015) | 2 lines

R600/SI: Don't crash when getting immediate operand size

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/SIInstrInfo.h

Modified: llvm/branches/release_36/lib/Target/R600/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstrInfo.h?rev=236022&r1=236021&r2=236022&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstrInfo.h (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstrInfo.h Tue Apr 28 14:12:20 2015
@@ -247,7 +247,27 @@ public:
   /// the register class of its machine operand.
   /// to infer the correct register class base on the other operands.
   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
-                                           unsigned OpNo) const;\
+                                           unsigned OpNo) const;
+
+  /// \brief Return the size in bytes of the operand OpNo on the given
+  // instruction opcode.
+  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
+    const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
+
+    if (OpInfo.RegClass == -1) {
+      // If this is an immediate operand, this must be a 32-bit literal.
+      assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
+      return 4;
+    }
+
+    return RI.getRegClass(OpInfo.RegClass)->getSize();
+  }
+
+  /// \brief This form should usually be preferred since it handles operands
+  /// with unknown register classes.
+  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
+    return getOpRegClass(MI, OpNo)->getSize();
+  }
 
   /// \returns true if it is legal for the operand at index \p OpNo
   /// to read a VGPR.





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