[llvm-branch-commits] [llvm-branch] r204649 - Merging r203281:

[Tom Stellard]

Author: tstellar
Date: Mon Mar 24 13:21:43 2014
New Revision: 204649

URL: http://llvm.org/viewvc/llvm-project?rev=204649&view=rev
Log:
Merging r203281:

------------------------------------------------------------------------
r203281 | thomas.stellard | 2014-03-07 12:12:39 -0800 (Fri, 07 Mar 2014) | 4 lines

R600/SI: Using SGPRs is illegal for instructions that read carry-out
from VCC

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>

Modified:
    llvm/branches/release_34/lib/Target/R600/SIInstrInfo.td
    llvm/branches/release_34/lib/Target/R600/SIInstructions.td

Modified: llvm/branches/release_34/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/SIInstrInfo.td?rev=204649&r1=204648&r2=204649&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/branches/release_34/lib/Target/R600/SIInstrInfo.td Mon Mar 24 13:21:43 2014
@@ -290,10 +290,10 @@ multiclass VOP2_64 <bits<6> op, string o
   : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>;
 
 multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
-                     string revOp = opName> {
+                     RegisterClass src0_rc, string revOp = opName> {
 
   def _e32 : VOP2 <
-    op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
+    op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1),
     opName#"_e32 $dst, $src0, $src1", pattern
   >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
 

Modified: llvm/branches/release_34/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/SIInstructions.td?rev=204649&r1=204648&r2=204649&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/SIInstructions.td (original)
+++ llvm/branches/release_34/lib/Target/R600/SIInstructions.td Mon Mar 24 13:21:43 2014
@@ -989,14 +989,16 @@ defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x000
 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
 // No patterns so that the scalar instructions are always selected.
 // The scalar versions will be replaced with vector when needed later.
-defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>;
-defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>;
-defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
+defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>;
+defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>;
+defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
+                              "V_SUB_I32">;
 
 let Uses = [VCC] in { // Carry-in comes from VCC
-defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
-defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
-defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
+defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>;
+defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>;
+defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
+                               "V_SUBB_U32">;
 } // End Uses = [VCC]
 } // End isCommutable = 1, Defs = [VCC]