[llvm-branch-commits] [llvm-branch] r164602 - in /llvm/branches/R600/lib/Target/AMDGPU: MCTargetDesc/R600MCCodeEmitter.cpp R600RegisterInfo.td SIRegisterInfo.td

[Tom Stellard]

Author: tstellar
Date: Tue Sep 25 08:59:13 2012
New Revision: 164602

URL: http://llvm.org/viewvc/llvm-project?rev=164602&view=rev
Log:
AMDGPU: Fix register encoding

The register encodings weren't being defined correctly in the .td files,
so they were all encoded as 0.

Modified:
    llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
    llvm/branches/R600/lib/Target/AMDGPU/R600RegisterInfo.td
    llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td

Modified: llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp?rev=164602&r1=164601&r2=164602&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp Tue Sep 25 08:59:13 2012
@@ -623,13 +623,7 @@
   }
 }
 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
-  unsigned HWReg;
-
-  HWReg = MRI.getEncodingValue(RegNo);
-  if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(RegNo)) {
-    HWReg += 512;
-  }
-  return HWReg;
+  return MRI.getEncodingValue(RegNo);
 }
 
 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,

Modified: llvm/branches/R600/lib/Target/AMDGPU/R600RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/R600RegisterInfo.td?rev=164602&r1=164601&r2=164602&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/R600RegisterInfo.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/R600RegisterInfo.td Tue Sep 25 08:59:13 2012
@@ -14,11 +14,11 @@
 foreach Index = 0-127 in {
   foreach Chan = [ "X", "Y", "Z", "W" ] in {
     // 32-bit Temporary Registers
-    def T#Index#_#Chan : R600Reg <"T"#Index#"."#Chan, !cast<bits<16>>(Index)>;
+    def T#Index#_#Chan : R600Reg <"T"#Index#"."#Chan, Index>;
 
     // 32-bit Constant Registers (There are more than 128, this the number
     // that is currently supported.
-    def C#Index#_#Chan : R600Reg <"C"#Index#"."#Chan, !cast<bits<16>>(Index)>;
+    def C#Index#_#Chan : R600Reg <"C"#Index#"."#Chan, Index>;
   }
   // 128-bit Temporary Registers
   def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
@@ -26,7 +26,7 @@
                                     !cast<Register>("T"#Index#"_Y"),
                                     !cast<Register>("T"#Index#"_Z"),
                                     !cast<Register>("T"#Index#"_W")],
-                                   !cast<bits<16>>(Index)>;
+                                   Index>;
 }
 
 // Special Registers

Modified: llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td?rev=164602&r1=164601&r2=164602&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td Tue Sep 25 08:59:13 2012
@@ -66,7 +66,7 @@
 
 // SGPR 32-bit registers
 foreach Index = 0-103 in {
-  def SGPR#Index : SGPR_32 <!cast<bits<16>>(Index), "SGPR"#Index>;
+  def SGPR#Index : SGPR_32 <Index, "SGPR"#Index>;
 }
 
 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
@@ -97,7 +97,7 @@
 
 // VGPR 32-bit registers
 foreach Index = 0-255 in {
-  def VGPR#Index : VGPR_32 <!cast<bits<16>>(Index), "VGPR"#Index>;
+  def VGPR#Index : VGPR_32 <Index, "VGPR"#Index>;
 }
 
 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,