[llvm-branch-commits] [llvm-branch] r164535 - in /llvm/branches/R600: lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp lib/Target/AMDGPU/R600ISelLowering.cpp lib/Target/AMDGPU/R600Instructions.td test/CodeGen/R600/store.v4f32.ll

[Tom Stellard]

Author: tstellar
Date: Mon Sep 24 10:52:47 2012
New Revision: 164535

URL: http://llvm.org/viewvc/llvm-project?rev=164535&view=rev
Log:
R600: Add support for v4f32 stores on R600

Added:
    llvm/branches/R600/test/CodeGen/R600/store.v4f32.ll
Modified:
    llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
    llvm/branches/R600/lib/Target/AMDGPU/R600ISelLowering.cpp
    llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td

Modified: llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp?rev=164535&r1=164534&r2=164535&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp Mon Sep 24 10:52:47 2012
@@ -156,7 +156,8 @@
     return;
   } else {
     switch(MI.getOpcode()) {
-    case AMDGPU::RAT_WRITE_CACHELESS_eg:
+    case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
+    case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
       {
         uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
         EmitByte(INSTR_NATIVE, OS);

Modified: llvm/branches/R600/lib/Target/AMDGPU/R600ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=164535&r1=164534&r2=164535&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/R600ISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/R600ISelLowering.cpp Mon Sep 24 10:52:47 2012
@@ -121,7 +121,8 @@
       return BB;
     }
 
-  case AMDGPU::RAT_WRITE_CACHELESS_eg:
+  case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
+  case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
     {
       // Convert to DWORD address
       unsigned NewAddr = MRI.createVirtualRegister(

Modified: llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td?rev=164535&r1=164534&r2=164535&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td Mon Sep 24 10:52:47 2012
@@ -954,10 +954,8 @@
 
 let usesCustomInserter = 1 in {
 
-def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
-  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
-  "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr, $eop",
-  []>
+class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name> : EG_CF_RAT <
+  0x57, 0x2, 0, (outs), ins, !strconcat(name, " $rw_gpr, $index_gpr, $eop"), []>
 {
   let RIM         = 0;
   // XXX: Have a separate instruction for non-indexed writes.
@@ -966,7 +964,7 @@
   let ELEM_SIZE   = 0;
 
   let ARRAY_SIZE  = 0;
-  let COMP_MASK   = 1;
+  let COMP_MASK   = comp_mask;
   let BURST_COUNT = 0;
   let VPM         = 0;
   let MARK        = 0;
@@ -975,16 +973,34 @@
 
 } // End usesCustomInserter = 1
 
+// 32-bit store
+def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
+  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
+  0x1, "RAT_WRITE_CACHELESS_32_eg"
+>;
+
 // i32 global_store
 def : Pat <
   (global_store (i32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
-  (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
+  (RAT_WRITE_CACHELESS_32_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
 >;
 
 // Floating point global_store
 def : Pat <
   (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
-  (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
+  (RAT_WRITE_CACHELESS_32_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
+>;
+
+//128-bit store
+def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
+  (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
+  0xf, "RAT_WRITE_CACHELESS_128"
+>;
+
+// v4f32 global store
+def : Pat <
+  (global_store (v4f32 R600_Reg128:$val), R600_TReg32_X:$ptr),
+  (RAT_WRITE_CACHELESS_128_eg R600_Reg128:$val, R600_TReg32_X:$ptr, 0)
 >;
 
 class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>

Added: llvm/branches/R600/test/CodeGen/R600/store.v4f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/store.v4f32.ll?rev=164535&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/store.v4f32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/store.v4f32.ll Mon Sep 24 10:52:47 2012
@@ -0,0 +1,9 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
+
+define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+  %1 = load <4 x float> addrspace(1) * %in
+  store <4 x float> %1, <4 x float> addrspace(1)* %out
+  ret void
+}