[llvm-branch-commits] [llvm-branch] r114289 - /llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp

Gabor Greif ggreif at gmail.com
Sat Sep 18 09:30:51 PDT 2010


Author: ggreif
Date: Sat Sep 18 11:30:50 2010
New Revision: 114289

URL: http://llvm.org/viewvc/llvm-project?rev=114289&view=rev
Log:
implement relaxation:

  and r1, r12, #7
  ...
  tst r1, #5
  beq -->

can be optimized to

  andS r1, r12, #7
  ...
  beq -->

because the narrower test mask always tests to
zero if a wider one already did

Modified:
    llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114289&r1=114288&r2=114289&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Sep 18 11:30:50 2010
@@ -1402,7 +1402,8 @@
     case ARM::ANDri:
     case ARM::t2ANDri:
       if (SrcReg == MI.getOperand(1).getReg() &&
-          CmpMask == MI.getOperand(2).getImm())
+          CmpMask == (MI.getOperand(2).getImm() &
+                      (Relaxable ? CmpMask : ~0)))
         return true;
   }
 





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