[llvm-branch-commits] [llvm-branch] r114288 - /llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp

[Gabor Greif]

Author: ggreif
Date: Sat Sep 18 11:04:11 2010
New Revision: 114288

URL: http://llvm.org/viewvc/llvm-project?rev=114288&view=rev
Log:
refactor: no functionality change besides addition of T2 ops

Modified:
    llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114288&r1=114287&r2=114288&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Sep 18 11:04:11 2010
@@ -1386,26 +1386,24 @@
     CmpValue = MI->getOperand(1).getImm();
     return true;
   case ARM::TSTri:
+  case ARM::t2TSTri:
     SrcReg = MI->getOperand(0).getReg();
     CmpMask = MI->getOperand(1).getImm();
     CmpValue = 0;
     return true;
-    /*
- {
-    MachineBasicBlock::const_iterator MII(MI);
-    if (MI->getParent()->begin() == MII)
-      return false;
-    const MachineInstr *AND = llvm::prior(MII);
-    if (AND->getOpcode() != ARM::ANDri)
-      return false;
-    if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
-        MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
-      SrcReg = AND->getOperand(0).getReg();
-      CmpValue = 0;
-      return true;
-    }
-    }
-    break;*/
+  }
+
+  return false;
+}
+
+static bool isSuitableForMask(const MachineInstr &MI, unsigned SrcReg,
+                              int CmpMask, bool Relaxable) {
+  switch (MI.getOpcode()) {
+    case ARM::ANDri:
+    case ARM::t2ANDri:
+      if (SrcReg == MI.getOperand(1).getReg() &&
+          CmpMask == MI.getOperand(2).getImm())
+        return true;
   }
 
   return false;
@@ -1427,26 +1425,22 @@
     return false;
 
   MachineInstr *MI = &*DI;
+
   // Masked compares sometimes use the same register as the corresponding 'and'.
   if (CmpMask != ~0) {
-    for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
-         UE = MRI.use_end(); UI != UE; ++UI) {
-			if (UI->getParent() != CmpInstr->getParent()) continue;
-      switch (UI->getOpcode()) {
-      case ARM::ANDri: {
-        MachineInstr &AND = *UI;
-        if (SrcReg == AND.getOperand(1).getReg() &&
-            CmpMask == AND.getOperand(2).getImm()) {
-          SrcReg = AND.getOperand(0).getReg();
-          MI = ∧
-          break;
-        }
-        continue;
-      }
-      default:
-        continue;
+    if (!isSuitableForMask(*MI, SrcReg, CmpMask, true)) {
+      MI = 0;
+      for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
+           UE = MRI.use_end(); UI != UE; ++UI) {
+        if (UI->getParent() != CmpInstr->getParent()) continue;
+        MachineInstr &PotentialAND = *UI;
+        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, false))
+          continue;
+        SrcReg = PotentialAND.getOperand(0).getReg();
+        MI = &PotentialAND;
+        break;
       }
-      break;
+      if (!MI) return false;
     }
   }