[llvm-branch-commits] [llvm-branch] r114290 - /llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp

[Gabor Greif]

Author: ggreif
Date: Sat Sep 18 11:44:10 2010
New Revision: 114290

URL: http://llvm.org/viewvc/llvm-project?rev=114290&view=rev
Log:
back out r114289, here is a counterexample:

mov r12, #1
and r1, r12, #3
tst r1, #2
beq -->

will not take the branch when
optimized to:

mov r12, #1
andS r1, r12, #3
beq -->

also simplify the code a bit,
now that relaxation is not an
option

Modified:
    llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114290&r1=114289&r2=114290&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Sep 18 11:44:10 2010
@@ -1397,13 +1397,12 @@
 }
 
 static bool isSuitableForMask(const MachineInstr &MI, unsigned SrcReg,
-                              int CmpMask, bool Relaxable) {
+                              int CmpMask) {
   switch (MI.getOpcode()) {
     case ARM::ANDri:
     case ARM::t2ANDri:
       if (SrcReg == MI.getOperand(1).getReg() &&
-          CmpMask == (MI.getOperand(2).getImm() &
-                      (Relaxable ? CmpMask : ~0)))
+          CmpMask == MI.getOperand(2).getImm())
         return true;
   }
 
@@ -1429,13 +1428,13 @@
 
   // Masked compares sometimes use the same register as the corresponding 'and'.
   if (CmpMask != ~0) {
-    if (!isSuitableForMask(*MI, SrcReg, CmpMask, true)) {
+    if (!isSuitableForMask(*MI, SrcReg, CmpMask)) {
       MI = 0;
       for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
            UE = MRI.use_end(); UI != UE; ++UI) {
         if (UI->getParent() != CmpInstr->getParent()) continue;
         MachineInstr &PotentialAND = *UI;
-        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, false))
+        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask))
           continue;
         SrcReg = PotentialAND.getOperand(0).getReg();
         MI = &PotentialAND;