[llvm-branch-commits] [llvm-branch] r103949 - in /llvm/branches/Apple/Morbo/lib: CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h
Evan Cheng
evan.cheng at apple.com
Mon May 17 10:42:47 PDT 2010
Author: evancheng
Date: Mon May 17 12:42:46 2010
New Revision: 103949
URL: http://llvm.org/viewvc/llvm-project?rev=103949&view=rev
Log:
Merge: 102111 102192.
Modified:
llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=103949&r1=103948&r2=103949&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 17 12:42:46 2010
@@ -130,6 +130,7 @@
bool CombineToPostIndexedLoadStore(SDNode *N);
SDValue PromoteIntBinOp(SDValue Op);
+ SDValue PromoteIntShiftOp(SDValue Op);
SDValue PromoteExtend(SDValue Op);
bool PromoteLoad(SDValue Op);
@@ -169,8 +170,6 @@
SDValue visitSHL(SDNode *N);
SDValue visitSRA(SDNode *N);
SDValue visitSRL(SDNode *N);
- SDValue visitROTL(SDNode *N);
- SDValue visitROTR(SDNode *N);
SDValue visitCTLZ(SDNode *N);
SDValue visitCTTZ(SDNode *N);
SDValue visitCTPOP(SDNode *N);
@@ -723,7 +722,47 @@
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
assert(PVT != VT && "Don't know what type to promote to!");
- bool isShift = (Opc == ISD::SHL) || (Opc == ISD::SRA) || (Opc == ISD::SRL);
+ SDValue N0 = PromoteOperand(Op.getOperand(0), PVT, DAG, TLI);
+ if (N0.getNode() == 0)
+ return SDValue();
+
+ SDValue N1 = PromoteOperand(Op.getOperand(1), PVT, DAG, TLI);
+ if (N1.getNode() == 0)
+ return SDValue();
+
+ AddToWorkList(N0.getNode());
+ AddToWorkList(N1.getNode());
+
+ DebugLoc dl = Op.getDebugLoc();
+ return DAG.getNode(ISD::TRUNCATE, dl, VT,
+ DAG.getNode(Opc, dl, PVT, N0, N1));
+ }
+ return SDValue();
+}
+
+/// PromoteIntShiftOp - Promote the specified integer shift operation if the
+/// target indicates it is beneficial. e.g. On x86, it's usually better to
+/// promote i16 operations to i32 since i16 instructions are longer.
+SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
+ if (!LegalOperations)
+ return SDValue();
+
+ EVT VT = Op.getValueType();
+ if (VT.isVector() || !VT.isInteger())
+ return SDValue();
+
+ // If operation type is 'undesirable', e.g. i16 on x86, consider
+ // promoting it.
+ unsigned Opc = Op.getOpcode();
+ if (TLI.isTypeDesirableForOp(Opc, VT))
+ return SDValue();
+
+ EVT PVT = VT;
+ // Consult target whether it is a good idea to promote this operation and
+ // what's the right type to promote it to.
+ if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
+ assert(PVT != VT && "Don't know what type to promote to!");
+
SDValue N0 = Op.getOperand(0);
if (Opc == ISD::SRA)
N0 = SExtPromoteOperand(Op.getOperand(0), PVT, DAG, TLI);
@@ -733,19 +772,11 @@
N0 = PromoteOperand(N0, PVT, DAG, TLI);
if (N0.getNode() == 0)
return SDValue();
-
- SDValue N1 = Op.getOperand(1);
- if (!isShift) {
- N1 = PromoteOperand(N1, PVT, DAG, TLI);
- if (N1.getNode() == 0)
- return SDValue();
- AddToWorkList(N1.getNode());
- }
AddToWorkList(N0.getNode());
DebugLoc dl = Op.getDebugLoc();
return DAG.getNode(ISD::TRUNCATE, dl, VT,
- DAG.getNode(Op.getOpcode(), dl, PVT, N0, N1));
+ DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
}
return SDValue();
}
@@ -953,8 +984,6 @@
case ISD::SHL: return visitSHL(N);
case ISD::SRA: return visitSRA(N);
case ISD::SRL: return visitSRL(N);
- case ISD::ROTL: return visitROTL(N);
- case ISD::ROTR: return visitROTR(N);
case ISD::CTLZ: return visitCTLZ(N);
case ISD::CTTZ: return visitCTTZ(N);
case ISD::CTPOP: return visitCTPOP(N);
@@ -2785,7 +2814,7 @@
return NewSHL;
}
- return PromoteIntBinOp(SDValue(N, 0));
+ return PromoteIntShiftOp(SDValue(N, 0));
}
SDValue DAGCombiner::visitSRA(SDNode *N) {
@@ -2905,7 +2934,7 @@
return NewSRA;
}
- return PromoteIntBinOp(SDValue(N, 0));
+ return PromoteIntShiftOp(SDValue(N, 0));
}
SDValue DAGCombiner::visitSRL(SDNode *N) {
@@ -3062,15 +3091,7 @@
}
}
- return PromoteIntBinOp(SDValue(N, 0));
-}
-
-SDValue DAGCombiner::visitROTL(SDNode *N) {
- return PromoteIntBinOp(SDValue(N, 0));
-}
-
-SDValue DAGCombiner::visitROTR(SDNode *N) {
- return PromoteIntBinOp(SDValue(N, 0));
+ return PromoteIntShiftOp(SDValue(N, 0));
}
SDValue DAGCombiner::visitCTLZ(SDNode *N) {
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp?rev=103949&r1=103948&r2=103949&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp Mon May 17 12:42:46 2010
@@ -5914,10 +5914,33 @@
return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
}
+// getSetCCPromoteOpcode - Return the opcode that should be used to promote
+// operands of a setcc. FIXME: See DAGTypeLegalizer::PromoteSetCCOperands.
+static unsigned getSetCCPromoteOpcode(ISD::CondCode CC) {
+ switch (CC) {
+ default: return 0;
+ case ISD::SETEQ:
+ case ISD::SETNE:
+ case ISD::SETUGE:
+ case ISD::SETUGT:
+ case ISD::SETULE:
+ case ISD::SETULT:
+ // ALL of these operations will work if we either sign or zero extend
+ // the operands (including the unsigned comparisons!). Zero extend is
+ // usually a simpler/cheaper operation, so prefer it.
+ return ISD::ZERO_EXTEND;
+ case ISD::SETGE:
+ case ISD::SETGT:
+ case ISD::SETLT:
+ case ISD::SETLE:
+ return ISD::SIGN_EXTEND;
+ }
+}
+
/// Emit nodes that will be selected as "test Op0,Op0", or something
/// equivalent.
SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
- SelectionDAG &DAG) {
+ ISD::CondCode CC, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// CF and OF aren't always set the way we want. Determine which
@@ -6046,8 +6069,13 @@
}
// Otherwise just emit a CMP with 0, which is the TEST pattern.
- if (Subtarget->shouldPromote16Bit() && Op.getValueType() == MVT::i16)
- Op = DAG.getNode(ISD::ANY_EXTEND, Op.getDebugLoc(), MVT::i32, Op);
+ EVT PVT;
+ if (Subtarget->shouldPromote16Bit() && Op.getValueType() == MVT::i16 &&
+ (isa<ConstantSDNode>(Op) || IsDesirableToPromoteOp(Op, PVT))) {
+ unsigned POpc = getSetCCPromoteOpcode(CC);
+ if (POpc)
+ Op = DAG.getNode(POpc, Op.getDebugLoc(), MVT::i32, Op);
+ }
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
DAG.getConstant(0, Op.getValueType()));
}
@@ -6055,15 +6083,21 @@
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent.
SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
- SelectionDAG &DAG) {
+ ISD::CondCode CC, SelectionDAG &DAG) {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
if (C->getAPIntValue() == 0)
- return EmitTest(Op0, X86CC, DAG);
+ return EmitTest(Op0, X86CC, CC, DAG);
DebugLoc dl = Op0.getDebugLoc();
- if (Subtarget->shouldPromote16Bit() && Op0.getValueType() == MVT::i16) {
- Op0 = DAG.getNode(ISD::ANY_EXTEND, Op0.getDebugLoc(), MVT::i32, Op0);
- Op1 = DAG.getNode(ISD::ANY_EXTEND, Op1.getDebugLoc(), MVT::i32, Op1);
+ EVT PVT;
+ if (Subtarget->shouldPromote16Bit() && Op0.getValueType() == MVT::i16 &&
+ (isa<ConstantSDNode>(Op0) || IsDesirableToPromoteOp(Op0, PVT)) &&
+ (isa<ConstantSDNode>(Op1) || IsDesirableToPromoteOp(Op1, PVT))) {
+ unsigned POpc = getSetCCPromoteOpcode(CC);
+ if (POpc) {
+ Op0 = DAG.getNode(POpc, Op0.getDebugLoc(), MVT::i32, Op0);
+ Op1 = DAG.getNode(POpc, Op1.getDebugLoc(), MVT::i32, Op1);
+ }
}
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
}
@@ -6166,7 +6200,7 @@
if (X86CC == X86::COND_INVALID)
return SDValue();
- SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
+ SDValue Cond = EmitCmp(Op0, Op1, X86CC, CC, DAG);
// Use sbb x, x to materialize carry bit into a GPR.
if (X86CC == X86::COND_B)
@@ -6399,7 +6433,7 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond = EmitTest(Cond, X86::COND_NE, DAG);
+ Cond = EmitTest(Cond, X86::COND_NE, ISD::SETNE, DAG);
}
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
@@ -6573,7 +6607,7 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond = EmitTest(Cond, X86::COND_NE, DAG);
+ Cond = EmitTest(Cond, X86::COND_NE, ISD::SETNE, DAG);
}
return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Chain, Dest, CC, Cond);
@@ -9976,8 +10010,6 @@
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
- case ISD::ROTL:
- case ISD::ROTR:
case ISD::SUB:
case ISD::ADD:
case ISD::MUL:
@@ -10021,9 +10053,7 @@
break;
case ISD::SHL:
case ISD::SRA:
- case ISD::SRL:
- case ISD::ROTL:
- case ISD::ROTR: {
+ case ISD::SRL: {
SDValue N0 = Op.getOperand(0);
// Look out for (store (shl (load), x)).
if (isa<LoadSDNode>(N0) && N0.hasOneUse() &&
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h?rev=103949&r1=103948&r2=103949&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h Mon May 17 12:42:46 2010
@@ -824,11 +824,12 @@
/// Emit nodes that will be selected as "test Op0,Op0", or something
/// equivalent, for use with the given x86 condition code.
- SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
+ SDValue EmitTest(SDValue Op0, unsigned X86CC, ISD::CondCode CC,
+ SelectionDAG &DAG);
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent, for use with the given x86 condition code.
- SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
+ SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, ISD::CondCode CC,
SelectionDAG &DAG);
};
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