Mon May 17 10:33:42 PDT 2010

Author: evancheng
Date: Mon May 17 12:33:42 2010
New Revision: 103947

URL: http://llvm.org/viewvc/llvm-project?rev=103947&view=rev
Log:
Merge: 101971, 101979.

Modified:
    llvm/branches/Apple/Morbo/include/llvm/CodeGen/LiveIntervalAnalysis.h
    llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.h
    llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h
    llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td
    llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp
    llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h
    llvm/branches/Apple/Morbo/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
    llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll
    llvm/branches/Apple/Morbo/test/CodeGen/X86/postra-licm.ll
    llvm/branches/Apple/Morbo/test/CodeGen/X86/stack-color-with-reg.ll

Modified: llvm/branches/Apple/Morbo/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================

--- llvm/branches/Apple/Morbo/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/branches/Apple/Morbo/include/llvm/CodeGen/LiveIntervalAnalysis.h Mon May 17 12:33:42 2010
@@ -111,6 +111,12 @@
     double getScaledIntervalSize(LiveInterval& I) {
       return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
     }
+
+    /// getFuncInstructionCount - Return the number of instructions in the
+    /// current function.
+    unsigned getFuncInstructionCount() {
+      return indexes_->getFunctionSize();
+    }
     
     /// getApproximateInstructionCount - computes an estimate of the number
     /// of instructions in a given LiveInterval.

Modified: llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon May 17 12:33:42 2010
@@ -1144,20 +1144,44 @@
 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
 /// two virtual registers from different register classes.
 bool
-SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
-                                                unsigned SmallReg,
-                                                unsigned Threshold) {
-  // Then make sure the intervals are *short*.
-  LiveInterval &LargeInt = li_->getInterval(LargeReg);
-  LiveInterval &SmallInt = li_->getInterval(SmallReg);
-  unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
-  unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
-  if (LargeSize > Threshold) {
-    unsigned SmallUses = std::distance(mri_->use_nodbg_begin(SmallReg),
-                                       mri_->use_nodbg_end());
-    unsigned LargeUses = std::distance(mri_->use_nodbg_begin(LargeReg),
-                                       mri_->use_nodbg_end());
-    if (SmallUses*LargeSize < LargeUses*SmallSize)
+SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
+                                                unsigned DstReg,
+                                             const TargetRegisterClass *SrcRC,
+                                             const TargetRegisterClass *DstRC,
+                                             const TargetRegisterClass *NewRC) {
+  unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
+  // This heuristics is good enough in practice, but it's obviously not *right*.
+  // 4 is a magic number that works well enough for x86, ARM, etc. It filter
+  // out all but the most restrictive register classes.
+  if (NewRCCount > 4 ||
+      // Early exit if the function is fairly small, coalesce aggressively if
+      // that's the case. For really special register classes with 3 or
+      // fewer registers, be a bit more careful.
+      (li_->getFuncInstructionCount() / NewRCCount) < 8)
+    return true;
+  LiveInterval &SrcInt = li_->getInterval(SrcReg);
+  LiveInterval &DstInt = li_->getInterval(DstReg);
+  unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
+  unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
+  if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
+    return true;
+  // Estimate *register use density*. If it doubles or more, abort.
+  unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
+                                   mri_->use_nodbg_end());
+  unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
+                                   mri_->use_nodbg_end());
+  float NewDensity = ((float)(SrcUses + DstUses) / (SrcSize + DstSize)) /
+    NewRCCount;
+  if (SrcRC != NewRC && SrcSize > NewRCCount) {
+    unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
+    float Density = ((float)SrcUses / SrcSize) / SrcRCCount;
+    if (NewDensity > Density * 2.0f)
+      return false;
+  }
+  if (DstRC != NewRC && DstSize > NewRCCount) {
+    unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
+    float Density = ((float)DstUses / DstSize) / DstRCCount;
+    if (NewDensity > Density * 2.0f)
       return false;
   }
   return true;
@@ -1500,10 +1524,11 @@
           return false;  // Not coalescable
         }
 
-        unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
-        unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
-        unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
-        if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
+        if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
+          DEBUG(dbgs() << "\tAvoid coalescing to constrainted register class: "
+                       << SrcRC->getName() << "/"
+                       << DstRC->getName() << " -> "
+                       << NewRC->getName() << ".\n");
           Again = true;  // May be possible to coalesce later.
           return false;
         }
@@ -1551,49 +1576,40 @@
       }
     }
 
-    unsigned LargeReg = SrcReg;
-    unsigned SmallReg = DstReg;
-
     // Now determine the register class of the joined register.
-    if (isExtSubReg) {
-      if (SubIdx && DstRC && DstRC->isASubClass()) {
-        // This is a move to a sub-register class. However, the source is a
-        // sub-register of a larger register class. We don't know what should
-        // the register class be. FIXME.
-        Again = true;
-        return false;
+    if (!SrcIsPhys && !DstIsPhys) {
+      if (isExtSubReg) {
+        NewRC =
+          SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC;
+      } else if (isInsSubReg) {
+        NewRC =
+          SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC;
+      } else {
+        NewRC = getCommonSubClass(SrcRC, DstRC);
       }
-      if (!DstIsPhys && !SrcIsPhys)
-        NewRC = SrcRC;
-    } else if (!SrcIsPhys && !DstIsPhys) {
-      NewRC = getCommonSubClass(SrcRC, DstRC);
+
       if (!NewRC) {
         DEBUG(dbgs() << "\tDisjoint regclasses: "
                      << SrcRC->getName() << ", "
                      << DstRC->getName() << ".\n");
         return false;           // Not coalescable.
       }
-      if (DstRC->getSize() > SrcRC->getSize())
-        std::swap(LargeReg, SmallReg);
-    }
 
-    // If we are joining two virtual registers and the resulting register
-    // class is more restrictive (fewer register, smaller size). Check if it's
-    // worth doing the merge.
-    if (!SrcIsPhys && !DstIsPhys &&
-        (isExtSubReg || DstRC->isASubClass()) &&
-        !isWinToJoinCrossClass(LargeReg, SmallReg,
-                               allocatableRCRegs_[NewRC].count())) {
-      DEBUG(dbgs() << "\tSrc/Dest are different register classes: "
-                   << SrcRC->getName() << "/"
-                   << DstRC->getName() << " -> "
-                   << NewRC->getName() << ".\n");
-      // Allow the coalescer to try again in case either side gets coalesced to
-      // a physical register that's compatible with the other side. e.g.
-      // r1024 = MOV32to32_ r1025
-      // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
-      Again = true;  // May be possible to coalesce later.
-      return false;
+      // If we are joining two virtual registers and the resulting register
+      // class is more restrictive (fewer register, smaller size). Check if it's
+      // worth doing the merge.
+      if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
+        DEBUG(dbgs() << "\tAvoid coalescing to constrainted register class: "
+                     << SrcRC->getName() << "/"
+                     << DstRC->getName() << " -> "
+                     << NewRC->getName() << ".\n");
+        // Allow the coalescer to try again in case either side gets coalesced to
+        // a physical register that's compatible with the other side. e.g.
+        // r1024 = MOV32to32_ r1025
+        // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
+        Again = true;  // May be possible to coalesce later.
+        return false;
+      }
     }
   }
 

Modified: llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.h?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.h (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/SimpleRegisterCoalescing.h Mon May 17 12:33:42 2010
@@ -179,8 +179,11 @@
 
     /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
     /// two virtual registers from different register classes.
-    bool isWinToJoinCrossClass(unsigned LargeReg, unsigned SmallReg,
-                               unsigned Threshold);
+    bool isWinToJoinCrossClass(unsigned SrcReg,
+                               unsigned DstReg,
+                               const TargetRegisterClass *SrcRC,
+                               const TargetRegisterClass *DstRC,
+                               const TargetRegisterClass *NewRC);
 
     /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
     /// register with a physical register, check if any of the virtual register

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp Mon May 17 12:33:42 2010
@@ -64,9 +64,6 @@
 static cl::opt<bool>
 Disable16Bit("disable-16bit", cl::Hidden,
              cl::desc("Disable use of 16-bit instructions"));
-static cl::opt<bool>
-Promote16Bit("promote-16bit", cl::Hidden,
-             cl::desc("Promote 16-bit instructions"));
 
 // Forward declarations.
 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
@@ -6049,7 +6046,7 @@
   }
 
   // Otherwise just emit a CMP with 0, which is the TEST pattern.
-  if (Promote16Bit && Op.getValueType() == MVT::i16)
+  if (Subtarget->shouldPromote16Bit() && Op.getValueType() == MVT::i16)
     Op = DAG.getNode(ISD::ANY_EXTEND, Op.getDebugLoc(), MVT::i32, Op);
   return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
                      DAG.getConstant(0, Op.getValueType()));
@@ -6064,7 +6061,7 @@
       return EmitTest(Op0, X86CC, DAG);
 
   DebugLoc dl = Op0.getDebugLoc();
-  if (Promote16Bit && Op0.getValueType() == MVT::i16) {
+  if (Subtarget->shouldPromote16Bit() && Op0.getValueType() == MVT::i16) {
     Op0 = DAG.getNode(ISD::ANY_EXTEND, Op0.getDebugLoc(), MVT::i32, Op0);
     Op1 = DAG.getNode(ISD::ANY_EXTEND, Op1.getDebugLoc(), MVT::i32, Op1);
   }
@@ -6073,8 +6070,8 @@
 
 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
 /// if it's possible.
-static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
-                         DebugLoc dl, SelectionDAG &DAG) {
+SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
+                                     DebugLoc dl, SelectionDAG &DAG) {
   SDValue Op0 = And.getOperand(0);
   SDValue Op1 = And.getOperand(1);
   if (Op0.getOpcode() == ISD::TRUNCATE)
@@ -6111,7 +6108,7 @@
     // the encoding for the i16 version is larger than the i32 version.
     // Also promote i16 to i32 for performance / code size reason.
     if (LHS.getValueType() == MVT::i8 ||
-        (Promote16Bit && LHS.getValueType() == MVT::i16))
+        (Subtarget->shouldPromote16Bit() && LHS.getValueType() == MVT::i16))
       LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
 
     // If the operand types disagree, extend the shift amount to match.  Since
@@ -9966,7 +9963,7 @@
 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
   if (!isTypeLegal(VT))
     return false;
-  if (!Promote16Bit || VT != MVT::i16)
+  if (!Subtarget->shouldPromote16Bit() || VT != MVT::i16)
     return true;
 
   switch (Opc) {
@@ -9995,7 +9992,7 @@
 /// beneficial for dag combiner to promote the specified node. If true, it
 /// should return the desired promotion type by reference.
 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
-  if (!Promote16Bit)
+  if (!Subtarget->shouldPromote16Bit())
     return false;
 
   EVT VT = Op.getValueType();

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h Mon May 17 12:33:42 2010
@@ -699,6 +699,8 @@
     SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
     SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
+    SDValue LowerToBT(SDValue And, ISD::CondCode CC,
+                      DebugLoc dl, SelectionDAG &DAG);
     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
     SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
@@ -720,7 +722,6 @@
     SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
     SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG);
     SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG);
-
     SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
     SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
     SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG);

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td Mon May 17 12:33:42 2010
@@ -329,6 +329,8 @@
 def FastBTMem    : Predicate<"!Subtarget->isBTMemSlow()">;
 def CallImmAddr  : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
 def HasAES       : Predicate<"Subtarget->hasAES()">;
+def Promote16Bit : Predicate<"Subtarget->shouldPromote16Bit()">;
+def NotPromote16Bit : Predicate<"!Subtarget->shouldPromote16Bit()">;
 
 //===----------------------------------------------------------------------===//
 // X86 Instruction Format Definitions.
@@ -4497,7 +4499,13 @@
 // avoid partial-register updates.
 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8  GR8 :$src)>;
 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8  GR8 :$src)>;
-def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
+def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>,
+          Requires<[NotPromote16Bit]>;
+
+def : Pat<(i32 (anyext GR16:$src)),
+          (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>,
+          Requires<[Promote16Bit]>;
+
 
 //===----------------------------------------------------------------------===//
 // Some peepholes

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp Mon May 17 12:33:42 2010
@@ -16,6 +16,7 @@
 #include "X86InstrInfo.h"
 #include "X86GenSubtarget.inc"
 #include "llvm/GlobalValue.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/System/Host.h"
@@ -24,6 +25,10 @@
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
 
+static cl::opt<bool>
+DoPromote16Bit("promote-16bit", cl::Hidden,
+               cl::desc("Promote 16-bit instructions"));
+
 #if defined(_MSC_VER)
 #include <intrin.h>
 #endif
@@ -293,6 +298,7 @@
   , IsBTMemSlow(false)
   , IsUAMemFast(false)
   , HasVectorUAMem(false)
+  , Promote16Bit(DoPromote16Bit)
   , DarwinVers(0)
   , stackAlignment(8)
   // FIXME: this is a known good value for Yonah. How about others?

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h Mon May 17 12:33:42 2010
@@ -85,10 +85,13 @@
   bool IsUAMemFast;
 
   /// HasVectorUAMem - True if SIMD operations can have unaligned memory
-  ///                  operands. This may require setting a feature bit in the
-  ///                  processor.
+  /// operands. This may require setting a feature bit in the processor.
   bool HasVectorUAMem;
 
+  /// Promote16Bit - True if codegen should promote 16-bit operations to 32-bit.
+  /// This is a temporary option.
+  bool Promote16Bit;
+
   /// DarwinVers - Nonzero if this is a darwin platform: the numeric
   /// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
   unsigned char DarwinVers; // Is any darwin-x86 platform.
@@ -157,6 +160,7 @@
   bool isBTMemSlow() const { return IsBTMemSlow; }
   bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
   bool hasVectorUAMem() const { return HasVectorUAMem; }
+  bool shouldPromote16Bit() const { return Promote16Bit; }
 
   bool isTargetDarwin() const { return TargetType == isDarwin; }
   bool isTargetELF() const { return TargetType == isELF; }

Modified: llvm/branches/Apple/Morbo/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll Mon May 17 12:33:42 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 3
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 1
 
 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind {
 entry:

Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll Mon May 17 12:33:42 2010
@@ -1,4 +1,5 @@
-; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edi}
+; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 40
+; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | FileCheck %s
 
 	%struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
 	%struct.XXDAlphaTest = type { float, i16, i8, i8 }
@@ -61,11 +62,15 @@
 
 define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind {
 entry:
+; CHECK: t:
+; CHECK: xorl %ecx, %ecx
 	%0 = trunc i64 %key_token to i32		; <i32> [#uses=1]
 	%1 = getelementptr %struct.YYToken* %pstrm, i32 %0		; <%struct.YYToken*> [#uses=5]
 	br label %bb1132
 
 bb51:		; preds = %bb1132
+; CHECK: .align 4
+; CHECK: andl $7
 	%2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0		; <i16*> [#uses=1]
 	%3 = load i16* %2, align 1		; <i16> [#uses=3]
 	%4 = lshr i16 %3, 6		; <i16> [#uses=1]

Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/postra-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/postra-licm.ll?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/postra-licm.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/postra-licm.ll Mon May 17 12:33:42 2010
@@ -149,7 +149,6 @@
 
 bb.nph:                                           ; preds = %entry
 ; X86-64: movq _map_4_to_16 at GOTPCREL(%rip)
-; X86-64: movq _map_4_to_16 at GOTPCREL(%rip)
 ; X86-64: .align 4
   %tmp5 = zext i32 undef to i64                   ; <i64> [#uses=1]
   %tmp6 = add i64 %tmp5, 1                        ; <i64> [#uses=1]

Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/stack-color-with-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/stack-color-with-reg.ll?rev=103947&r1=103946&r2=103947&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/stack-color-with-reg.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/stack-color-with-reg.ll Mon May 17 12:33:42 2010
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
-; RUN:   grep asm-printer %t | grep 156
-; RUN:   grep stackcoloring %t | grep "stack slot refs replaced with reg refs"  | grep 4
+; RUN:   grep asm-printer %t | grep 166
+; RUN:   grep stackcoloring %t | grep "stack slot refs replaced with reg refs"  | grep 5
 
 	type { [62 x %struct.Bitvec*] }		; type %0
 	type { i8* }		; type %1



