[llvm-branch-commits] [llvm-branch] r103951 - in /llvm/branches/Apple/Morbo/lib: CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h
Evan Cheng
evan.cheng at apple.com
Mon May 17 10:47:32 PDT 2010
Author: evancheng
Date: Mon May 17 12:47:32 2010
New Revision: 103951
URL: http://llvm.org/viewvc/llvm-project?rev=103951&view=rev
Log:
Merge 102202 102236 102237 102366.
Modified:
llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=103951&r1=103950&r2=103951&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 17 12:47:32 2010
@@ -129,6 +129,10 @@
bool CombineToPreIndexedLoadStore(SDNode *N);
bool CombineToPostIndexedLoadStore(SDNode *N);
+ void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
+ SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
+ SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
+ SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
SDValue PromoteIntBinOp(SDValue Op);
SDValue PromoteIntShiftOp(SDValue Op);
SDValue PromoteExtend(SDValue Op);
@@ -636,17 +640,31 @@
return true;
}
-static SDValue SExtPromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
- const TargetLowering &TLI);
-static SDValue ZExtPromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
- const TargetLowering &TLI);
+void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
+ DebugLoc dl = Load->getDebugLoc();
+ EVT VT = Load->getValueType(0);
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
-static SDValue PromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
- const TargetLowering &TLI) {
+ DEBUG(dbgs() << "\nReplacing.9 ";
+ Load->dump(&DAG);
+ dbgs() << "\nWith: ";
+ Trunc.getNode()->dump(&DAG);
+ dbgs() << '\n');
+ WorkListRemover DeadNodes(*this);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
+ &DeadNodes);
+ removeFromWorkList(Load);
+ DAG.DeleteNode(Load);
+}
+
+SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
+ Replace = false;
DebugLoc dl = Op.getDebugLoc();
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
ISD::LoadExtType ExtType =
ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD : LD->getExtensionType();
+ Replace = true;
return DAG.getExtLoad(ExtType, dl, PVT,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
@@ -655,48 +673,55 @@
}
unsigned Opc = Op.getOpcode();
- if (Opc == ISD::AssertSext)
+ switch (Opc) {
+ default: break;
+ case ISD::AssertSext:
return DAG.getNode(ISD::AssertSext, dl, PVT,
- SExtPromoteOperand(Op.getOperand(0), PVT, DAG, TLI),
+ SExtPromoteOperand(Op.getOperand(0), PVT),
Op.getOperand(1));
- else if (Opc == ISD::AssertZext)
+ case ISD::AssertZext:
return DAG.getNode(ISD::AssertZext, dl, PVT,
- ZExtPromoteOperand(Op.getOperand(0), PVT, DAG, TLI),
+ ZExtPromoteOperand(Op.getOperand(0), PVT),
Op.getOperand(1));
-
- unsigned ExtOpc = ISD::ANY_EXTEND;
- if (Opc == ISD::Constant)
- // Zero extend things like i1, sign extend everything else. It shouldn't
- // matter in theory which one we pick, but this tends to give better code?
- // See DAGTypeLegalizer::PromoteIntRes_Constant.
- ExtOpc =
+ case ISD::Constant: {
+ unsigned ExtOpc =
Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- if (!TLI.isOperationLegal(ExtOpc, PVT))
+ return DAG.getNode(ExtOpc, dl, PVT, Op);
+ }
+ }
+
+ if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
return SDValue();
- return DAG.getNode(ExtOpc, dl, PVT, Op);
+ return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
}
-static SDValue SExtPromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
- const TargetLowering &TLI) {
+SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
return SDValue();
EVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- Op = PromoteOperand(Op, PVT, DAG, TLI);
- if (Op.getNode() == 0)
+ bool Replace = false;
+ SDValue NewOp = PromoteOperand(Op, PVT, Replace);
+ if (NewOp.getNode() == 0)
return SDValue();
- return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
+
+ if (Replace)
+ ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
DAG.getValueType(OldVT));
}
-static SDValue ZExtPromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
- const TargetLowering &TLI) {
+SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
EVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- Op = PromoteOperand(Op, PVT, DAG, TLI);
- if (Op.getNode() == 0)
+ bool Replace = false;
+ SDValue NewOp = PromoteOperand(Op, PVT, Replace);
+ if (NewOp.getNode() == 0)
return SDValue();
- return DAG.getZeroExtendInReg(Op, dl, OldVT);
+
+ if (Replace)
+ ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
+ return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
}
/// PromoteIntBinOp - Promote the specified integer binary operation if the
@@ -722,20 +747,29 @@
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
assert(PVT != VT && "Don't know what type to promote to!");
- SDValue N0 = PromoteOperand(Op.getOperand(0), PVT, DAG, TLI);
- if (N0.getNode() == 0)
+ bool Replace0 = false;
+ SDValue N0 = Op.getOperand(0);
+ SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
+ if (NN0.getNode() == 0)
return SDValue();
- SDValue N1 = PromoteOperand(Op.getOperand(1), PVT, DAG, TLI);
- if (N1.getNode() == 0)
+ bool Replace1 = false;
+ SDValue N1 = Op.getOperand(1);
+ SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
+ if (NN1.getNode() == 0)
return SDValue();
- AddToWorkList(N0.getNode());
- AddToWorkList(N1.getNode());
+ AddToWorkList(NN0.getNode());
+ AddToWorkList(NN1.getNode());
+
+ if (Replace0)
+ ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
+ if (Replace1)
+ ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
DebugLoc dl = Op.getDebugLoc();
return DAG.getNode(ISD::TRUNCATE, dl, VT,
- DAG.getNode(Opc, dl, PVT, N0, N1));
+ DAG.getNode(Opc, dl, PVT, NN0, NN1));
}
return SDValue();
}
@@ -763,16 +797,20 @@
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
assert(PVT != VT && "Don't know what type to promote to!");
+ bool Replace = false;
SDValue N0 = Op.getOperand(0);
if (Opc == ISD::SRA)
- N0 = SExtPromoteOperand(Op.getOperand(0), PVT, DAG, TLI);
+ N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
else if (Opc == ISD::SRL)
- N0 = ZExtPromoteOperand(Op.getOperand(0), PVT, DAG, TLI);
+ N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
else
- N0 = PromoteOperand(N0, PVT, DAG, TLI);
+ N0 = PromoteOperand(N0, PVT, Replace);
if (N0.getNode() == 0)
return SDValue();
+
AddToWorkList(N0.getNode());
+ if (Replace)
+ ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
DebugLoc dl = Op.getDebugLoc();
return DAG.getNode(ISD::TRUNCATE, dl, VT,
@@ -840,9 +878,9 @@
LD->isNonTemporal(), LD->getAlignment());
SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
- DEBUG(dbgs() << "\nReplacing.x ";
+ DEBUG(dbgs() << "\nPromoting ";
N->dump(&DAG);
- dbgs() << "\nWith: ";
+ dbgs() << "\nTo: ";
Result.getNode()->dump(&DAG);
dbgs() << '\n');
WorkListRemover DeadNodes(*this);
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp?rev=103951&r1=103950&r2=103951&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp Mon May 17 12:47:32 2010
@@ -5914,33 +5914,10 @@
return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
}
-// getSetCCPromoteOpcode - Return the opcode that should be used to promote
-// operands of a setcc. FIXME: See DAGTypeLegalizer::PromoteSetCCOperands.
-static unsigned getSetCCPromoteOpcode(ISD::CondCode CC) {
- switch (CC) {
- default: return 0;
- case ISD::SETEQ:
- case ISD::SETNE:
- case ISD::SETUGE:
- case ISD::SETUGT:
- case ISD::SETULE:
- case ISD::SETULT:
- // ALL of these operations will work if we either sign or zero extend
- // the operands (including the unsigned comparisons!). Zero extend is
- // usually a simpler/cheaper operation, so prefer it.
- return ISD::ZERO_EXTEND;
- case ISD::SETGE:
- case ISD::SETGT:
- case ISD::SETLT:
- case ISD::SETLE:
- return ISD::SIGN_EXTEND;
- }
-}
-
/// Emit nodes that will be selected as "test Op0,Op0", or something
/// equivalent.
SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
- ISD::CondCode CC, SelectionDAG &DAG) {
+ SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// CF and OF aren't always set the way we want. Determine which
@@ -6069,13 +6046,6 @@
}
// Otherwise just emit a CMP with 0, which is the TEST pattern.
- EVT PVT;
- if (Subtarget->shouldPromote16Bit() && Op.getValueType() == MVT::i16 &&
- (isa<ConstantSDNode>(Op) || IsDesirableToPromoteOp(Op, PVT))) {
- unsigned POpc = getSetCCPromoteOpcode(CC);
- if (POpc)
- Op = DAG.getNode(POpc, Op.getDebugLoc(), MVT::i32, Op);
- }
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
DAG.getConstant(0, Op.getValueType()));
}
@@ -6083,22 +6053,12 @@
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent.
SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
- ISD::CondCode CC, SelectionDAG &DAG) {
+ SelectionDAG &DAG) {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
if (C->getAPIntValue() == 0)
- return EmitTest(Op0, X86CC, CC, DAG);
+ return EmitTest(Op0, X86CC, DAG);
DebugLoc dl = Op0.getDebugLoc();
- EVT PVT;
- if (Subtarget->shouldPromote16Bit() && Op0.getValueType() == MVT::i16 &&
- (isa<ConstantSDNode>(Op0) || IsDesirableToPromoteOp(Op0, PVT)) &&
- (isa<ConstantSDNode>(Op1) || IsDesirableToPromoteOp(Op1, PVT))) {
- unsigned POpc = getSetCCPromoteOpcode(CC);
- if (POpc) {
- Op0 = DAG.getNode(POpc, Op0.getDebugLoc(), MVT::i32, Op0);
- Op1 = DAG.getNode(POpc, Op1.getDebugLoc(), MVT::i32, Op1);
- }
- }
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
}
@@ -6200,7 +6160,7 @@
if (X86CC == X86::COND_INVALID)
return SDValue();
- SDValue Cond = EmitCmp(Op0, Op1, X86CC, CC, DAG);
+ SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
// Use sbb x, x to materialize carry bit into a GPR.
if (X86CC == X86::COND_B)
@@ -6433,7 +6393,7 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond = EmitTest(Cond, X86::COND_NE, ISD::SETNE, DAG);
+ Cond = EmitTest(Cond, X86::COND_NE, DAG);
}
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
@@ -6607,7 +6567,7 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond = EmitTest(Cond, X86::COND_NE, ISD::SETNE, DAG);
+ Cond = EmitTest(Cond, X86::COND_NE, DAG);
}
return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Chain, Dest, CC, Cond);
@@ -10020,6 +9980,14 @@
}
}
+static bool MayFoldLoad(SDValue Op) {
+ return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
+}
+
+static bool MayFoldIntoStore(SDValue Op) {
+ return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
+}
+
/// IsDesirableToPromoteOp - This method query the target whether it is
/// beneficial for dag combiner to promote the specified node. If true, it
/// should return the desired promotion type by reference.
@@ -10056,8 +10024,7 @@
case ISD::SRL: {
SDValue N0 = Op.getOperand(0);
// Look out for (store (shl (load), x)).
- if (isa<LoadSDNode>(N0) && N0.hasOneUse() &&
- Op.hasOneUse() && Op.getNode()->use_begin()->getOpcode() == ISD::STORE)
+ if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
return false;
Promote = true;
break;
@@ -10072,12 +10039,12 @@
case ISD::SUB: {
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
- if (!Commute && isa<LoadSDNode>(N1))
+ if (!Commute && MayFoldLoad(N1))
return false;
// Avoid disabling potential load folding opportunities.
- if ((isa<LoadSDNode>(N0) && N0.hasOneUse()) && !isa<ConstantSDNode>(N1))
+ if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
return false;
- if ((isa<LoadSDNode>(N1) && N1.hasOneUse()) && !isa<ConstantSDNode>(N0))
+ if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
return false;
Promote = true;
}
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h?rev=103951&r1=103950&r2=103951&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.h Mon May 17 12:47:32 2010
@@ -824,12 +824,11 @@
/// Emit nodes that will be selected as "test Op0,Op0", or something
/// equivalent, for use with the given x86 condition code.
- SDValue EmitTest(SDValue Op0, unsigned X86CC, ISD::CondCode CC,
- SelectionDAG &DAG);
+ SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent, for use with the given x86 condition code.
- SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, ISD::CondCode CC,
+ SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
SelectionDAG &DAG);
};
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