[llvm-branch-commits] [llvm-branch] r84593 - in /llvm/branches/Apple/Leela: include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/RegisterScavenging.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMRegisterInfo.td lib/Target/ARM/README-Thumb.txt lib/Target/ARM/Thumb1RegisterInfo.cpp lib/Target/ARM/Thumb1RegisterInfo.h test/CodeGen/Thumb/2009-08-20-ISelBug.ll
Bill Wendling
isanbard at gmail.com
Mon Oct 19 21:04:18 PDT 2009
Author: void
Date: Mon Oct 19 23:04:17 2009
New Revision: 84593
URL: http://llvm.org/viewvc/llvm-project?rev=84593&view=rev
Log:
$ svn merge -c 84554 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84554 into '.':
U include/llvm/Target/TargetRegisterInfo.h
U lib/CodeGen/RegisterScavenging.cpp
U lib/Target/ARM/Thumb1RegisterInfo.cpp
U lib/Target/ARM/Thumb1RegisterInfo.h
$ svn merge -c 84563 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84563 into '.':
U test/CodeGen/Thumb/2009-08-20-ISelBug.ll
G lib/Target/ARM/Thumb1RegisterInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
U lib/Target/ARM/README-Thumb.txt
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
$ svn merge -c 84570 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84570 into '.':
U lib/Target/ARM/ARMInstrFormats.td
$ svn merge -c 84572 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84572 into '.':
U lib/Target/ARM/ARMInstrNEON.td
G lib/Target/ARM/ARMInstrFormats.td
Modified:
llvm/branches/Apple/Leela/include/llvm/Target/TargetRegisterInfo.h
llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td
llvm/branches/Apple/Leela/lib/Target/ARM/README-Thumb.txt
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h
llvm/branches/Apple/Leela/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetRegisterInfo.h?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetRegisterInfo.h Mon Oct 19 23:04:17 2009
@@ -641,24 +641,17 @@
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
}
- /// saveScavengerRegister - Save the register so it can be used by the
- /// register scavenger. Return true if the register was saved, false
- /// otherwise. If this function does not save the register, the scavenger
+ /// saveScavengerRegister - Spill the register so it can be used by the
+ /// register scavenger. Return true if the register was spilled, false
+ /// otherwise. If this function does not spill the register, the scavenger
/// will instead spill it to the emergency spill slot.
///
virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator &UseMI,
const TargetRegisterClass *RC,
unsigned Reg) const {return false;}
- /// restoreScavengerRegister - Restore a register saved by
- /// saveScavengerRegister().
- ///
- virtual void restoreScavengerRegister(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- const TargetRegisterClass *RC,
- unsigned Reg) const {}
-
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
/// frame indices from instructions which may use them. The instruction
/// referenced by the iterator contains an MO_FrameIndex operand which must be
Modified: llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp Mon Oct 19 23:04:17 2009
@@ -300,7 +300,7 @@
// If the target knows how to save/restore the register, let it do so;
// otherwise, use the emergency stack spill slot.
- if (!TRI->saveScavengerRegister(*MBB, I, RC, SReg)) {
+ if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
// Spill the scavenged register before I.
assert(ScavengingFrameIndex >= 0 &&
"Cannot scavenge register without an emergency spill slot!");
@@ -310,8 +310,7 @@
// Restore the scavenged register before its use (or first terminator).
TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC);
- } else
- TRI->restoreScavengerRegister(*MBB, UseMI, RC, SReg);
+ }
ScavengeRestore = prior(UseMI);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Oct 19 23:04:17 2009
@@ -740,8 +740,7 @@
case ARM::R1:
return ARM::R0;
case ARM::R3:
- // FIXME!
- return STI.isThumb1Only() ? 0 : ARM::R2;
+ return ARM::R2;
case ARM::R5:
return ARM::R4;
case ARM::R7:
@@ -830,8 +829,7 @@
case ARM::R0:
return ARM::R1;
case ARM::R2:
- // FIXME!
- return STI.isThumb1Only() ? 0 : ARM::R3;
+ return ARM::R3;
case ARM::R4:
return ARM::R5;
case ARM::R6:
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td Mon Oct 19 23:04:17 2009
@@ -1220,6 +1220,10 @@
string asm, string cstr, list<dag> pattern>
: NeonI<oops, iops, AddrMode6, IndexModeNone, itin, asm, cstr, pattern> {
let Inst{31-24} = 0b11110100;
+ let Inst{23} = op23;
+ let Inst{21-20} = op21_20;
+ let Inst{11-8} = op11_8;
+ let Inst{7-4} = op7_4;
}
class NDataI<dag oops, dag iops, InstrItinClass itin,
@@ -1286,6 +1290,20 @@
let Inst{4} = op4;
}
+// NEON 3 vector register with immediate. This is only used for VEXT where
+// op11_8 represents the starting byte index of the extracted result in the
+// concatenation of the operands and is left unspecified.
+class N3VImm<bit op24, bit op23, bits<2> op21_20, bit op6, bit op4,
+ dag oops, dag iops, InstrItinClass itin,
+ string asm, string cstr, list<dag> pattern>
+ : NDataI<oops, iops, itin, asm, cstr, pattern> {
+ let Inst{24} = op24;
+ let Inst{23} = op23;
+ let Inst{21-20} = op21_20;
+ let Inst{6} = op6;
+ let Inst{4} = op4;
+}
+
// NEON VMOVs between scalar and core registers.
class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
dag oops, dag iops, Format f, InstrItinClass itin,
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td Mon Oct 19 23:04:17 2009
@@ -2670,18 +2670,18 @@
// VEXT : Vector Extract
class VEXTd<string OpcodeStr, ValueType Ty>
- : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
- (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
- !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
- [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
- (Ty DPR:$rhs), imm:$index)))]>;
+ : N3VImm<0,1,0b11,0,0, (outs DPR:$dst),
+ (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
+ !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
+ [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
+ (Ty DPR:$rhs), imm:$index)))]>;
class VEXTq<string OpcodeStr, ValueType Ty>
- : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
- (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
- !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
- [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
- (Ty QPR:$rhs), imm:$index)))]>;
+ : N3VImm<0,1,0b11,1,0, (outs QPR:$dst),
+ (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
+ !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
+ [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
+ (Ty QPR:$rhs), imm:$index)))]>;
def VEXTd8 : VEXTd<"vext.8", v8i8>;
def VEXTd16 : VEXTd<"vext.16", v4i16>;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td Mon Oct 19 23:04:17 2009
@@ -222,12 +222,9 @@
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
- // FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it
- // to generate large stack offset. Make it available once we have register
- // scavenging.
let MethodBodies = [{
static const unsigned THUMB_tGPR_AO[] = {
- ARM::R0, ARM::R1, ARM::R2,
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
// FP is R7, only low registers available.
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/README-Thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/README-Thumb.txt?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/README-Thumb.txt (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/README-Thumb.txt Mon Oct 19 23:04:17 2009
@@ -196,14 +196,6 @@
objects are referenced off the frame pointer with negative offsets. See
oggenc for an example.
-//===---------------------------------------------------------------------===//
-
-We are reserving R3 as a scratch register under thumb mode. So if it is live in
-to the function, we save / restore R3 to / from R12. Until register scavenging
-is done, we should save R3 to a high callee saved reg at emitPrologue time
-(when hasFP is true or stack size is large) and restore R3 from that register
-instead. This allows us to at least get rid of the save to r12 everytime it is
-used.
//===---------------------------------------------------------------------===//
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Oct 19 23:04:17 2009
@@ -394,31 +394,48 @@
return 0;
}
-/// saveScavengerRegister - Save the register so it can be used by the
+/// saveScavengerRegister - Spill the register so it can be used by the
/// register scavenger. Return true.
-bool Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- const TargetRegisterClass *RC,
- unsigned Reg) const {
+bool
+Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator &UseMI,
+ const TargetRegisterClass *RC,
+ unsigned Reg) const {
// Thumb1 can't use the emergency spill slot on the stack because
// ldr/str immediate offsets must be positive, and if we're referencing
// off the frame pointer (if, for example, there are alloca() calls in
// the function, the offset will be negative. Use R12 instead since that's
// a call clobbered register that we know won't be used in Thumb1 mode.
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
+ addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
+
+ // The UseMI is where we would like to restore the register. If there's
+ // interference with R12 before then, however, we'll need to restore it
+ // before that instead and adjust the UseMI.
+ bool done = false;
+ for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
+ // If this instruction affects R12, adjust our restore point.
+ for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = II->getOperand(i);
+ if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
+ TargetRegisterInfo::isVirtualRegister(MO.getReg()))
+ continue;
+ if (MO.getReg() == ARM::R12) {
+ UseMI = II;
+ done = true;
+ break;
+ }
+ }
+ }
+ // Restore the register from R12
+ BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
+ addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
- TII.copyRegToReg(MBB, I, ARM::R12, Reg, ARM::GPRRegisterClass, RC);
return true;
}
-/// restoreScavengerRegister - restore a registers saved by
-// saveScavengerRegister().
-void Thumb1RegisterInfo::restoreScavengerRegister(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- const TargetRegisterClass *RC,
- unsigned Reg) const {
- TII.copyRegToReg(MBB, I, Reg, ARM::R12, RC, ARM::GPRRegisterClass);
-}
-
unsigned
Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, int *Value,
@@ -828,7 +845,6 @@
if (VARegSaveSize) {
// Epilogue for vararg functions: pop LR to R3 and branch off it.
- // FIXME: Verify this is still ok when R3 is no longer being reserved.
AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
.addReg(0) // No write back.
.addReg(ARM::R3, RegState::Define);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h Mon Oct 19 23:04:17 2009
@@ -57,12 +57,9 @@
bool saveScavengerRegister(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator &UseMI,
const TargetRegisterClass *RC,
unsigned Reg) const;
- void restoreScavengerRegister(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- const TargetRegisterClass *RC,
- unsigned Reg) const;
unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, int *Value = NULL,
RegScavenger *RS = NULL) const;
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb/2009-08-20-ISelBug.ll?rev=84593&r1=84592&r2=84593&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb/2009-08-20-ISelBug.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb/2009-08-20-ISelBug.ll Mon Oct 19 23:04:17 2009
@@ -11,7 +11,7 @@
define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
; CHECK: t:
-; CHECK: adds r4, #8
+; CHECK: adds r3, #8
entry:
%val = alloca i64, align 4 ; <i64*> [#uses=3]
%0 = icmp eq %struct.asl_file_t* %s, null ; <i1> [#uses=1]
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